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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2016-10-04 13:28:10 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-10-04 13:28:10 +0100
commit173ff58580b383a7841b18fddb293038c9d40d1c (patch)
treef7a1d6c382da891a88b172df38877deb2ae68732 /README
parent79b2ac8f28748b09816d09bd62a2b49ddc01ebeb (diff)
target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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