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authorPaolo Bonzini <pbonzini@redhat.com>2024-07-01 21:11:07 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2024-10-31 18:28:33 +0100
commitcea677e821c5d4efad5e25e504e935751fa61c95 (patch)
treeacc018dcc4d7f99757c172b7fe7bd9cd2eb19ec5
parent37df7c4d577124e01f087f598842b253aa2c9eca (diff)
target/i386: add a few more trivial CCPrepare cases
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--target/i386/tcg/translate.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d3bbcf7317..6e89d4faef 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -993,6 +993,7 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2,
.no_setcond = true };
+ case CC_OP_LOGICB ... CC_OP_LOGICQ:
case CC_OP_POPCNT:
return (CCPrepare) { .cond = TCG_COND_NEVER };
case CC_OP_MULB ... CC_OP_MULQ:
@@ -1021,6 +1022,8 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
}
gen_helper_cc_compute_nz(reg, cpu_cc_dst, cpu_cc_src, cpu_cc_op);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = reg, .imm = 0 };
+ case CC_OP_POPCNT:
+ return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst };
default:
{
MemOp size = cc_op_size(s->cc_op);