diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-06-25 20:31:43 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-26 14:32:24 +0100 |
| commit | c7459633baa71d1781fde4a245d6ec9ce2f008cf (patch) | |
| tree | 8fcac39b4f2b3fb01fcf0a8a643c95ae12937ee8 | |
| parent | e4d5bf4fbd5abfc3727e711eda64a583cab4d637 (diff) | |
target/arm: Enable MTE
We now implement all of the components of MTE, without actually
supporting any tagged memory. All MTE instructions will work,
trivially, so we can enable support.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu64.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a0c1d8894b..a2f4733eed 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,6 +654,11 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + /* + * Begin with full support for MTE; will be downgraded to MTE=1 + * during realize if the board provides no tag memory. + */ + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1; |