diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-07 21:25:42 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 17:02:34 +0200 |
| commit | bc3551c43308dd77bc1cc9a4e39962b2afd4dffc (patch) | |
| tree | c28068a87ee64f3c82e60b992ccbc54b57e97ecd | |
| parent | e5c96c82bc529674b61eacd221734abc2674e264 (diff) | |
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-tricore/translate.c | 10 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 52f474ba9f..4aea0c632a 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -7792,10 +7792,12 @@ static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) { uint32_t op2; + uint32_t r1; TCGLabel *l1; TCGv tmp; op2 = MASK_OP_SYS_OP2(ctx->opcode); + r1 = MASK_OP_SYS_S1D(ctx->opcode); switch (op2) { case OPC2_32_SYS_DEBUG: @@ -7844,6 +7846,14 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_SYS_SVLCX: gen_helper_svlcx(cpu_env); break; + case OPC2_32_SYS_RESTORE: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || + (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { + tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); + } /* else raise privilege trap */ + } /* else raise illegal opcode trap */ + break; case OPC2_32_SYS_TRAPSV: /* TODO: raise sticky overflow trap */ break; diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 440c7fefed..d1506a9429 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1434,4 +1434,5 @@ enum { OPC2_32_SYS_SVLCX = 0x08, OPC2_32_SYS_TRAPSV = 0x15, OPC2_32_SYS_TRAPV = 0x14, + OPC2_32_SYS_RESTORE = 0x0e, }; |