diff options
author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-09-11 16:00:05 +0200 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-07 08:33:01 +1000 |
commit | bb4dc158e084c3293b553c37f3ace99997aeff6f (patch) | |
tree | e0fd6f810fe611894b1f01f14dfd1a90b6a46346 | |
parent | 878dd0e9ac18af657dcbdb598bb2eb1278606d3a (diff) |
target/riscv: Reassign instructions to the Zba-extension
The following instructions are part of Zba:
- add.uw (RV64 only)
- sh[123]add (RV32 and RV64)
- sh[123]add.uw (RV64-only)
- slli.uw (RV64-only)
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | target/riscv/insn32.decode | 20 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 16 |
2 files changed, 23 insertions, 13 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2cd921d51c..86f1166dab 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -660,6 +660,18 @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm +# *** RV32 Zba Standard Extension *** +sh1add 0010000 .......... 010 ..... 0110011 @r +sh2add 0010000 .......... 100 ..... 0110011 @r +sh3add 0010000 .......... 110 ..... 0110011 @r + +# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** +add_uw 0000100 .......... 000 ..... 0111011 @r +sh1add_uw 0010000 .......... 010 ..... 0111011 @r +sh2add_uw 0010000 .......... 100 ..... 0111011 @r +sh3add_uw 0010000 .......... 110 ..... 0111011 @r +slli_uw 00001 ............ 001 ..... 0011011 @sh + # *** RV32B Standard Extension *** clz 011000 000000 ..... 001 ..... 0010011 @r2 ctz 011000 000001 ..... 001 ..... 0010011 @r2 @@ -687,9 +699,6 @@ ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r -sh1add 0010000 .......... 010 ..... 0110011 @r -sh2add 0010000 .......... 100 ..... 0110011 @r -sh3add 0010000 .......... 110 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -718,10 +727,6 @@ rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sh1add_uw 0010000 .......... 010 ..... 0111011 @r -sh2add_uw 0010000 .......... 100 ..... 0111011 @r -sh3add_uw 0010000 .......... 110 ..... 0111011 @r -add_uw 0000100 .......... 000 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -732,4 +737,3 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 -slli_uw 00001. ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 73d1e45026..fd549c7b0f 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -1,8 +1,9 @@ /* - * RISC-V translation routines for the RVB Standard Extension. + * RISC-V translation routines for the RVB draft and Zba Standard Extension. * * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,6 +18,11 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ +#define REQUIRE_ZBA(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \ + return false; \ + } \ +} while (0) static void gen_clz(TCGv ret, TCGv arg1) { @@ -339,7 +345,7 @@ GEN_SHADD(3) #define GEN_TRANS_SHADD(SHAMT) \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \ { \ - REQUIRE_EXT(ctx, RVB); \ + REQUIRE_ZBA(ctx); \ return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \ } @@ -616,7 +622,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ arg_sh##SHAMT##add_uw *a) \ { \ REQUIRE_64BIT(ctx); \ - REQUIRE_EXT(ctx, RVB); \ + REQUIRE_ZBA(ctx); \ return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \ } @@ -635,7 +641,7 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); return gen_arith(ctx, a, EXT_NONE, gen_add_uw); } @@ -647,6 +653,6 @@ static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt) static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) { REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); + REQUIRE_ZBA(ctx); return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw); } |