diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2024-01-24 12:55:49 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-02-09 20:43:14 +1000 |
| commit | afa42c21b5984bb9846e498bb00b1bdc28f56ab5 (patch) | |
| tree | c6ec73a3fab093425df8fa33226ac179586b7188 | |
| parent | 79b50e2c80e50391b7f06b275fbc11f9a4ee168a (diff) | |
target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS
A cpu may not have the same xlen as the compile time target, and
misa_mxl_max is the source of truth for what the hart supports.
The conversion from misa_mxl_max to xlen already has one user, so
introduce a helper and use that to populate the isa string.
Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-swear-monthly-56c281f809a6@spud>
[ Changes by AF:
- Convert to use RISCVCPUClass *mcc
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 10 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 | ||||
| -rw-r--r-- | target/riscv/gdbstub.c | 2 |
3 files changed, 11 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 84902be070..7fc45660d7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -308,6 +308,11 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) env->misa_ext_mask = env->misa_ext = ext; } +int riscv_cpu_max_xlen(RISCVCPUClass *mcc) +{ + return 16 << mcc->misa_mxl_max; +} + #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -2357,10 +2362,13 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, char *riscv_isa_string(RISCVCPU *cpu) { + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); int i; const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); char *isa_str = g_new(char, maxlen); - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); + int xlen = riscv_cpu_max_xlen(mcc); + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); + for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { *p++ = qemu_tolower(riscv_single_letter_exts[i]); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 285a247368..9bc14056fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -511,6 +511,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); +int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(const char *optname); #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 0ae0c47df1..ca9b71f7bb 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -221,7 +221,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = 16 << mcc->misa_mxl_max; + int bitsize = riscv_cpu_max_xlen(mcc); int i; #if !defined(CONFIG_USER_ONLY) |