diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-13 12:37:12 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-25 13:02:14 +0200 |
| commit | 98d207cf9c232e6ac451b2aba24baa007956f578 (patch) | |
| tree | 8f31d442112fc7ae0095553edb0199c5aaab8ca4 | |
| parent | bf7720024c62c9e2707b11aa7fe178be691b2f35 (diff) | |
target/mips: Document Loongson-3A CPU definitions
Document the cores on which each Loongson-3A CPU is based (see
commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-2-f4bug@amsat.org>
| -rw-r--r-- | target/mips/cpu-defs.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998c..c6ab3af190 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -805,7 +805,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A1000", + .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */ .CP0_PRid = 0x6305, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -835,7 +835,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", /* GS464V-based */ + .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |