diff options
| author | KONRAD Frederic <frederic.konrad@adacore.com> | 2017-08-01 10:44:57 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-08-09 11:46:44 +1000 |
| commit | 89fca22f212bd9000e9b481bd70dceb8df2a17a0 (patch) | |
| tree | 0fb2e7718b271bf7cf4880049d7a880966fc2470 | |
| parent | 54affb3a3623b1d36c95e34faa722a5831323a74 (diff) | |
booke206: fix MAS update on tlb miss
When a tlb instruction miss happen, rw is set to 0 at the bottom
of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target/ppc/mmu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index b7b9088842..f06b9382b4 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, env->spr[SPR_40x_ESR] = 0x00000000; break; case POWERPC_MMU_BOOKE206: - booke206_update_mas_tlb_miss(env, address, rw); + booke206_update_mas_tlb_miss(env, address, 2); /* fall through */ case POWERPC_MMU_BOOKE: cs->exception_index = POWERPC_EXCP_ITLB; |