diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-15 15:51:49 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-25 13:02:14 +0200 |
| commit | 78bdd3886577ce4f3e573685b155622e19bcca38 (patch) | |
| tree | 9ff7afdbcff8bda87faeb8dc6051da5209f59032 | |
| parent | 53152abfc148ebfb7843ef3596f4be5bc8e5eff9 (diff) | |
target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
$rt register is used read-only, so we can replace tcg_const_i32()
temporary by tcg_constant_i32().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/translate.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4b689a54ab..a6df9beb67 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -9072,12 +9072,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - { - TCGv_i32 fs_tmp = tcg_const_i32(rd); - - gen_helper_0e2i(ctc1, t0, fs_tmp, rt); - tcg_temp_free_i32(fs_tmp); - } + gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); /* Stop translation as we may have changed hflags */ ctx->base.is_jmp = DISAS_STOP; break; @@ -9694,12 +9689,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) case OPC_CTC1: gen_load_gpr(t0, rt); save_cpu_state(ctx, 0); - { - TCGv_i32 fs_tmp = tcg_const_i32(fs); - - gen_helper_0e2i(ctc1, t0, fs_tmp, rt); - tcg_temp_free_i32(fs_tmp); - } + gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); /* Stop translation as we may have changed hflags */ ctx->base.is_jmp = DISAS_STOP; break; |