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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-23 17:04:27 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-23 17:04:27 +0000
commit7385ac0ba2456159a52b9b2cbb5f6c71921d0c23 (patch)
treefe3ae4e3c3e3007c5f820e3eb7c92da4a1875cc7
parentd8a5950a62ee91d7fd8ed5ba459992b55e9cb3b7 (diff)
Use the standard ASE check for MIPS-3D and MT.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3427 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat
-rw-r--r--target-mips/mips-defs.h2
-rw-r--r--target-mips/translate.c169
-rw-r--r--target-mips/translate_init.c2
3 files changed, 80 insertions, 93 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 5c98edf974..a30f2edae1 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -32,6 +32,8 @@
#define ASE_MDMX 0x00004000
#define ASE_DSP 0x00008000
#define ASE_DSPR2 0x00010000
+#define ASE_MT 0x00020000
+#define ASE_SMARTMIPS 0x00040000
/* Chip specific instructions. */
/* Currently void */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 014a430e49..3a1f65c4c3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -749,12 +749,6 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx)
generate_exception(ctx, EXCP_RI);
}
-static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx)
-{
- if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D))))
- generate_exception(ctx, EXCP_RI);
-}
-
/*
* Verify if floating point register is valid; an operation is not defined
* if bit 0 of any register specification is set and the FR bit in the
@@ -780,14 +774,6 @@ static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags
generate_exception(ctx, EXCP_RI);
}
-/* This code generates a "reserved instruction" exception if the
- CPU is not MIPS MT capable. */
-static always_inline void check_mips_mt(CPUState *env, DisasContext *ctx)
-{
- if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
- generate_exception(ctx, EXCP_RI);
-}
-
/* This code generates a "reserved instruction" exception if 64-bit
instructions are not enabled. */
static always_inline void check_mips_64(DisasContext *ctx)
@@ -1971,17 +1957,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Index";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpcontrol();
rn = "MVPControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpconf0();
rn = "MVPConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpconf1();
rn = "MVPConf1";
break;
@@ -1996,37 +1982,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Random";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpecontrol();
rn = "VPEControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeconf0();
rn = "VPEConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeconf1();
rn = "VPEConf1";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_yqmask();
rn = "YQMask";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeschedule();
rn = "VPESchedule";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeschefback();
rn = "VPEScheFBack";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeopt();
rn = "VPEOpt";
break;
@@ -2041,37 +2027,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "EntryLo0";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcstatus();
rn = "TCStatus";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcbind();
rn = "TCBind";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcrestart();
rn = "TCRestart";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tchalt();
rn = "TCHalt";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tccontext();
rn = "TCContext";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcschedule();
rn = "TCSchedule";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcschefback();
rn = "TCScheFBack";
break;
@@ -2539,17 +2525,17 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Index";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_mvpcontrol();
rn = "MVPControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
/* ignored */
rn = "MVPConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
/* ignored */
rn = "MVPConf1";
break;
@@ -2564,37 +2550,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Random";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpecontrol();
rn = "VPEControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeconf0();
rn = "VPEConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeconf1();
rn = "VPEConf1";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_yqmask();
rn = "YQMask";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeschedule();
rn = "VPESchedule";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeschefback();
rn = "VPEScheFBack";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeopt();
rn = "VPEOpt";
break;
@@ -2609,37 +2595,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "EntryLo0";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcstatus();
rn = "TCStatus";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcbind();
rn = "TCBind";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcrestart();
rn = "TCRestart";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tchalt();
rn = "TCHalt";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tccontext();
rn = "TCContext";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcschedule();
rn = "TCSchedule";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcschefback();
rn = "TCScheFBack";
break;
@@ -3139,17 +3125,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Index";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpcontrol();
rn = "MVPControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpconf0();
rn = "MVPConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_mvpconf1();
rn = "MVPConf1";
break;
@@ -3164,37 +3150,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Random";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpecontrol();
rn = "VPEControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeconf0();
rn = "VPEConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeconf1();
rn = "VPEConf1";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_yqmask();
rn = "YQMask";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_vpeschedule();
rn = "VPESchedule";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_vpeschefback();
rn = "VPEScheFBack";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_vpeopt();
rn = "VPEOpt";
break;
@@ -3209,37 +3195,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "EntryLo0";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcstatus();
rn = "TCStatus";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mfc0_tcbind();
rn = "TCBind";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_tcrestart();
rn = "TCRestart";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_tchalt();
rn = "TCHalt";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_tccontext();
rn = "TCContext";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_tcschedule();
rn = "TCSchedule";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmfc0_tcschefback();
rn = "TCScheFBack";
break;
@@ -3696,17 +3682,17 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Index";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_mvpcontrol();
rn = "MVPControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
/* ignored */
rn = "MVPConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
/* ignored */
rn = "MVPConf1";
break;
@@ -3721,37 +3707,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "Random";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpecontrol();
rn = "VPEControl";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeconf0();
rn = "VPEConf0";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeconf1();
rn = "VPEConf1";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_yqmask();
rn = "YQMask";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeschedule();
rn = "VPESchedule";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeschefback();
rn = "VPEScheFBack";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_vpeopt();
rn = "VPEOpt";
break;
@@ -3766,37 +3752,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
rn = "EntryLo0";
break;
case 1:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcstatus();
rn = "TCStatus";
break;
case 2:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcbind();
rn = "TCBind";
break;
case 3:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcrestart();
rn = "TCRestart";
break;
case 4:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tchalt();
rn = "TCHalt";
break;
case 5:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tccontext();
rn = "TCContext";
break;
case 6:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcschedule();
rn = "TCSchedule";
break;
case 7:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_mtc0_tcschefback();
rn = "TCScheFBack";
break;
@@ -4636,7 +4622,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
break;
#endif
case OPC_MFTR:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
if (rd == 0) {
/* Treat as NOP. */
return;
@@ -4647,7 +4633,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
opn = "mftr";
break;
case OPC_MTTR:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
GEN_LOAD_REG_TN(T0, rt);
gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1,
ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
@@ -5893,7 +5879,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
/* MDMX extension to MIPS64 */
-/* MIPS-3D extension to MIPS64 */
#endif
@@ -6133,13 +6118,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
GEN_STORE_TN_REG(rt, T0);
break;
case OPC_FORK:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
GEN_LOAD_REG_TN(T0, rt);
GEN_LOAD_REG_TN(T1, rs);
gen_op_fork();
break;
case OPC_YIELD:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
GEN_LOAD_REG_TN(T0, rs);
gen_op_yield();
GEN_STORE_TN_REG(rd, T0);
@@ -6219,19 +6204,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dmt();
break;
case OPC_EMT:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_emt();
break;
case OPC_DVPE:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_dvpe();
break;
case OPC_EVPE:
- check_mips_mt(env, ctx);
+ check_insn(env, ctx, ASE_MT);
gen_op_evpe();
break;
case OPC_DI:
@@ -6336,7 +6321,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
- check_cp1_3d(env, ctx);
+ check_insn(env, ctx, ASE_MIPS3D);
/* fall through */
case OPC_BC1:
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 748b9dd85a..55c935e6d5 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -199,7 +199,7 @@ static mips_def_t mips_defs[] =
.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
},
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
{
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-24 23:36:22 +0000