diff options
| author | Alistair Francis <alistair23@gmail.com> | 2024-01-08 10:13:28 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
| commit | 71b76da33a1558bcd59100188f5753737ef6fa21 (patch) | |
| tree | 22701e05835602a7875548ed878c2ce9a675474a | |
| parent | 1525d8aa3a56610e1c72f5dd305ec86ebad41769 (diff) | |
target/riscv: Ensure mideleg is set correctly on reset
Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is
enabled. We currently only set them on accesses to mideleg, but they
aren't correctly set on reset. Let's ensure they are always the correct
value.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1617
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-4-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b32681f7f3..8cbfc7e781 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -932,6 +932,14 @@ static void riscv_cpu_reset_hold(Object *obj) env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); /* + * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor + * extension is enabled. + */ + if (riscv_has_ext(env, RVH)) { + env->mideleg |= HS_MODE_INTERRUPTS; + } + + /* * Clear mseccfg and unlock all the PMP entries upon reset. * This is allowed as per the priv and smepmp specifications * and is needed to clear stale entries across reboots. |