diff options
author | Song Gao <gaosong@loongson.cn> | 2023-05-25 20:00:05 +0800 |
---|---|---|
committer | Song Gao <gaosong@loongson.cn> | 2023-05-26 17:21:16 +0800 |
commit | 65bfaaae6ac79ebc623acc0ce28cc3bd4fe8b5e5 (patch) | |
tree | e85c77c95723c712515603c7157809a035b7ec52 | |
parent | 2e2ca3c8fa52c03c3725edfdd726972a223b74f3 (diff) |
target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump
The vinsgr2vr/vpickve2gr instructions need use get_src/get_dst to get
gpr registers value, not cpu_gpr[]. The $zero register does not
have cpu_gpr[0] allocated.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1662
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230525120005.2223413-1-gaosong@loongson.cn>
-rw-r--r-- | target/loongarch/insn_trans/trans_lsx.c.inc | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 0be2b5a3a8..68779daff6 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -3963,106 +3963,119 @@ TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d) static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st8_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm))); return true; } static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st16_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm))); return true; } static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st32_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm))); return true; } static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm))); return true; } static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld8s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); return true; } static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld16s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); return true; } static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld32s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); return true; } static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld8u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); return true; } static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld16u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); return true; } static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld32u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); return true; } static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd), - 16, ctx->vl/8, cpu_gpr[a->rj]); + 16, ctx->vl/8, src); return true; } |