diff options
| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2024-08-02 15:24:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-08-06 14:18:41 +1000 |
| commit | 5e54b439f5be1e604453d9b02d85685a266121da (patch) | |
| tree | 6f87d0eef0dfb4a767a0305bf58fdf08d38fd0b5 | |
| parent | 30d24145da72dc3f64d9d720ac2befad28e1daa2 (diff) | |
target/riscv: Relax fld alignment requirement
According to the risc-v specification:
"FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLEN≥64."
We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does
not violate the rules. But it will hide some problems. So relax it to
MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240802072417.659-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvd.c.inc | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 49682292b8..8a46124f98 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -48,11 +48,17 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_EXT(ctx, RVD); /* - * Zama16b applies to loads and stores of no more than MXLEN bits defined - * in the F, D, and Q extensions. + * FLD and FSD are only guaranteed to execute atomically if the effective + * address is naturally aligned and XLEN≥64. Also, zama16b applies to + * loads and stores of no more than MXLEN bits defined in the F, D, and + * Q extensions. */ - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) == MXL_RV32) { + memop |= MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ATOM_IFALIGN; } decode_save_opc(ctx); @@ -71,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); - if ((get_xl_max(ctx) >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { + if (get_xl_max(ctx) == MXL_RV32) { + memop |= MO_ATOM_NONE; + } else if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; + } else { + memop |= MO_ATOM_IFALIGN; } decode_save_opc(ctx); |