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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-10 01:05:01 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-10 01:05:01 +0000
commit59795a1f92ed81b63612edd41323792e81d2af7a (patch)
treeff0cb42bd9bcd8508b4c1f39d626220602719b75
parent2576d836af8386199873b774ee5dfdf03015a6b0 (diff)
x86 CPUID extended family/model (Andre Przywara).
x86 CPUs feature extended family/model bits in CPUID leaf 0000_0001|EAX. Refer to page 10 in: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf Those bits are necessary to model newer AMD CPUs: -cpu qemu64,family=15,model=65,stepping=3 or -cpu qemu64,family=16,model=4,stepping=2 Signed-off-by: Andre Przywara <andre.przywara@amd.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5664 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-i386/helper.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 4b8c503798..7ddb4cec13 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -337,7 +337,7 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
} else if (!strcmp(featurestr, "model")) {
char *err;
model = strtol(val, &err, 10);
- if (!*val || *err || model < 0 || model > 0xf) {
+ if (!*val || *err || model < 0 || model > 0xff) {
fprintf(stderr, "bad numerical value %s\n", val);
goto error;
}
@@ -416,7 +416,12 @@ static int cpu_x86_register (CPUX86State *env, const char *cpu_model)
env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
}
env->cpuid_level = def->level;
- env->cpuid_version = (def->family << 8) | (def->model << 4) | def->stepping;
+ if (def->family > 0x0f)
+ env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20);
+ else
+ env->cpuid_version = def->family << 8;
+ env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
+ env->cpuid_version |= def->stepping;
env->cpuid_features = def->features;
env->pat = 0x0007040600070406ULL;
env->cpuid_ext_features = def->ext_features;