diff options
| author | Richard Henderson <rth@twiddle.net> | 2016-11-16 11:17:45 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:11 -0800 |
| commit | 555baef8d0369fea9d0849ef420841665639c209 (patch) | |
| tree | efa17e16c2b3e06eb84b4cb68f9fa277ee8f9181 | |
| parent | 1a0196c5c7f197fad7b079074d587b3204bcfb0f (diff) | |
target-openrisc: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target/openrisc/helper.h | 2 | ||||
| -rw-r--r-- | target/openrisc/int_helper.c | 19 | ||||
| -rw-r--r-- | target/openrisc/translate.c | 6 |
3 files changed, 4 insertions, 23 deletions
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index f53fa21344..bcc7245fc3 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -54,8 +54,6 @@ FOP_CMP(ge) #undef FOP_CMP /* int */ -DEF_HELPER_FLAGS_1(ff1, 0, tl, tl) -DEF_HELPER_FLAGS_1(fl1, 0, tl, tl) DEF_HELPER_FLAGS_3(mul32, 0, i32, env, i32, i32) /* interrupt */ diff --git a/target/openrisc/int_helper.c b/target/openrisc/int_helper.c index 4d1f958901..ba0fd277cd 100644 --- a/target/openrisc/int_helper.c +++ b/target/openrisc/int_helper.c @@ -24,25 +24,6 @@ #include "exception.h" #include "qemu/host-utils.h" -target_ulong HELPER(ff1)(target_ulong x) -{ -/*#ifdef TARGET_OPENRISC64 - return x ? ctz64(x) + 1 : 0; -#else*/ - return x ? ctz32(x) + 1 : 0; -/*#endif*/ -} - -target_ulong HELPER(fl1)(target_ulong x) -{ -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - return 64 - clz64(x); -#else*/ - return 32 - clz32(x); -/*#endif*/ -} - uint32_t HELPER(mul32)(CPUOpenRISCState *env, uint32_t ra, uint32_t rb) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 229361aed1..03fa7db570 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -602,11 +602,13 @@ static void dec_calc(DisasContext *dc, uint32_t insn) switch (op1) { case 0x00: /* l.ff1 */ LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_ff1(cpu_R[rd], cpu_R[ra]); + tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); + tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); break; case 0x01: /* l.fl1 */ LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_fl1(cpu_R[rd], cpu_R[ra]); + tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); + tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); break; default: |