target/mips: Rename 'rtype' as 'r'

We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-5-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

6 files changed, 46 insertions, 46 deletions

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index bf132e36b9..74d99f6862 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -11,11 +11,11 @@
 #       - The MIPS64 SIMD Architecture Module, Revision 1.12
 #         (Document Number: MD00868-1D-MSA64-AFP-01.12)
 
-&rtype              rs rt rd sa
+&r                  rs rt rd sa
 
 &msa_bz             df wt s16
 
-@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &rtype
+@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 @bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
 @bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
 
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index eed2eca6c9..8170a8df26 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -2261,12 +2261,12 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
     return true;
 }
 
-static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
 
-static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_DLSA(DisasContext *ctx, arg_r *a)
 {
     if (TARGET_LONG_BITS != 64) {
         return false;
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index ed069c5166..d6989cf56e 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -14,9 +14,9 @@
 #       The MIPS64 Instruction Set Reference Manual, Revision 6.06
 #       (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
 
-&rtype              rs rt rd sa
+&r                  rs rt rd sa
 
-@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &rtype
+@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index ae2e023a81..d631851258 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -23,12 +23,12 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
     return true;
 }
 
-static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_LSA(DisasContext *ctx, arg_r *a)
 {
     return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
 
-static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+static bool trans_DLSA(DisasContext *ctx, arg_r *a)
 {
     if (TARGET_LONG_BITS != 64) {
         return false;
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 03a25a5096..57d87a2076 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -11,20 +11,20 @@
 # when creating helpers common to those for the individual
 # instruction patterns.
 
-&rtype           rs rt rd sa
+&r               rs rt rd sa
 
-&itype           base rt offset
+&i               base rt offset
 
 ###########################################################################
 # Named instruction formats.  These are generally used to
 # reduce the amount of duplication between instruction patterns.
 
-@rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &rtype sa=0
-@rt_rd          ...... ..... rt:5  rd:5  ..... ......   &rtype rs=0 sa=0
-@rs             ...... rs:5  ..... ..........  ......   &rtype rt=0 rd=0 sa=0
-@rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
+@rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &r sa=0
+@rt_rd          ...... ..... rt:5  rd:5  ..... ......   &r sa=0 rs=0
+@rs             ...... rs:5  ..... ..........  ......   &r sa=0      rt=0 rd=0
+@rd             ...... ..........  rd:5  ..... ......   &r sa=0 rs=0 rt=0
 
-@ldst            ...... base:5 rt:5 offset:16            &itype
+@ldst            ...... base:5 rt:5 offset:16           &i
 
 ###########################################################################
 
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 395d6afa1f..6d51fe17c1 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -64,28 +64,28 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
  * MTLO1   rs                Move To LO1 Register
  */
 
-static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MFHI1(DisasContext *ctx, arg_r *a)
 {
     gen_store_gpr(cpu_HI[1], a->rd);
 
     return true;
 }
 
-static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MFLO1(DisasContext *ctx, arg_r *a)
 {
     gen_store_gpr(cpu_LO[1], a->rd);
 
     return true;
 }
 
-static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MTHI1(DisasContext *ctx, arg_r *a)
 {
     gen_load_gpr(cpu_HI[1], a->rs);
 
     return true;
 }
 
-static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
+static bool trans_MTLO1(DisasContext *ctx, arg_r *a)
 {
     gen_load_gpr(cpu_LO[1], a->rs);
 
@@ -116,7 +116,7 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
  * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
  */
 
-static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
+static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
                                  void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
 {
     TCGv_i64 ax, bx;
@@ -146,19 +146,19 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a,
 }
 
 /* Parallel Subtract Byte */
-static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBB(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64);
 }
 
 /* Parallel Subtract Halfword */
-static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBH(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64);
 }
 
 /* Parallel Subtract Word */
-static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PSUBW(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64);
 }
@@ -189,25 +189,25 @@ static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
  */
 
 /* Parallel And */
-static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
+static bool trans_PAND(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_and_i64);
 }
 
 /* Parallel Or */
-static bool trans_POR(DisasContext *ctx, arg_rtype *a)
+static bool trans_POR(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_or_i64);
 }
 
 /* Parallel Exclusive Or */
-static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
+static bool trans_PXOR(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_xor_i64);
 }
 
 /* Parallel Not Or */
-static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
+static bool trans_PNOR(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_arith(ctx, a, tcg_gen_nor_i64);
 }
@@ -237,7 +237,7 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
  * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
  */
 
-static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
+static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
                                    TCGCond cond, unsigned wlen)
 {
     TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
@@ -286,37 +286,37 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
 }
 
 /* Parallel Compare for Greater Than Byte */
-static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTB(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_GE, 8);
 }
 
 /* Parallel Compare for Equal Byte */
-static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQB(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
 }
 
 /* Parallel Compare for Greater Than Halfword */
-static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTH(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_GE, 16);
 }
 
 /* Parallel Compare for Equal Halfword */
-static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQH(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
 }
 
 /* Parallel Compare for Greater Than Word */
-static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCGTW(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_GE, 32);
 }
 
 /* Parallel Compare for Equal Word */
-static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PCEQW(DisasContext *ctx, arg_r *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32);
 }
@@ -334,7 +334,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
  * SQ      rt, offset(base)  Store Quadword
  */
 
-static bool trans_LQ(DisasContext *ctx, arg_itype *a)
+static bool trans_LQ(DisasContext *ctx, arg_i *a)
 {
     TCGv_i64 t0;
     TCGv addr;
@@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
     return true;
 }
 
-static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+static bool trans_SQ(DisasContext *ctx, arg_i *a)
 {
     TCGv_i64 t0 = tcg_temp_new_i64();
     TCGv addr = tcg_temp_new();
@@ -437,7 +437,7 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a)
  */
 
 /* Parallel Pack to Word */
-static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PPACW(DisasContext *ctx, arg_r *a)
 {
     TCGv_i64 a0, b0, t0;
 
@@ -473,7 +473,7 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
     tcg_gen_deposit_i64(dh, a, b, 0, 32);
 }
 
-static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
 {
     TCGv_i64 ax, bx;
 
@@ -514,19 +514,19 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
 }
 
 /* Parallel Extend Lower from Byte */
-static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLB(DisasContext *ctx, arg_r *a)
 {
     return trans_PEXTLx(ctx, a, 8);
 }
 
 /* Parallel Extend Lower from Halfword */
-static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLH(DisasContext *ctx, arg_r *a)
 {
     return trans_PEXTLx(ctx, a, 16);
 }
 
 /* Parallel Extend Lower from Word */
-static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
 {
     TCGv_i64 ax, bx;
 
@@ -549,7 +549,7 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
 }
 
 /* Parallel Extend Upper from Word */
-static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
+static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
 {
     TCGv_i64 ax, bx;
 
@@ -593,7 +593,7 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
  */
 
 /* Parallel Copy Halfword */
-static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYH(DisasContext *s, arg_r *a)
 {
     if (a->rd == 0) {
         /* nop */
@@ -615,7 +615,7 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
 }
 
 /* Parallel Copy Lower Doubleword */
-static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYLD(DisasContext *s, arg_r *a)
 {
     if (a->rd == 0) {
         /* nop */
@@ -638,7 +638,7 @@ static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
 }
 
 /* Parallel Copy Upper Doubleword */
-static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
+static bool trans_PCPYUD(DisasContext *s, arg_r *a)
 {
     if (a->rd == 0) {
         /* nop */
@@ -657,7 +657,7 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
 }
 
 /* Parallel Rotate 3 Words Left */
-static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
+static bool trans_PROT3W(DisasContext *ctx, arg_r *a)
 {
     TCGv_i64 ax;