diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2021-06-01 15:31:38 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-06-04 13:47:08 +0200 |
| commit | 28f6aa1178581c3647819e1abc4905899d97d3a2 (patch) | |
| tree | 8ec87f28c83963d62b524ffb2bd1426127c9e813 | |
| parent | 29c3d213f4ad69688638330728cff1a8769d7415 (diff) | |
target/i386: tcg: fix segment register offsets for 16-bit TSS
The TSS offsets in the manuals have only 2-byte slots for the
segment registers. QEMU incorrectly uses 4-byte slots, so
that SS overlaps the LDT selector.
Resolves: #382
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/tcg/seg_helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 2f6cdc8239..547b959689 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -281,7 +281,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector, retaddr) | 0xffff0000; } for (i = 0; i < 4; i++) { - new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 4), + new_segs[i] = cpu_lduw_kernel_ra(env, tss_base + (0x22 + i * 2), retaddr); } new_ldt = cpu_lduw_kernel_ra(env, tss_base + 0x2a, retaddr); @@ -349,7 +349,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector, cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI], retaddr); cpu_stw_kernel_ra(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI], retaddr); for (i = 0; i < 4; i++) { - cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 4), + cpu_stw_kernel_ra(env, env->tr.base + (0x22 + i * 2), env->segs[i].selector, retaddr); } } |