diff options
author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-10-26 14:15:26 -0300 |
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committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-03 05:49:12 -0300 |
commit | 1b63c0b7a5879f7bbea4740697932706446b1ad9 (patch) | |
tree | 705833970973b42a74e0155daff278c4e30d1d44 | |
parent | 5d3d52229b19509eaace662096a52dc91f712fc1 (diff) |
target/mips: Extract decode_64bit_enabled() helper
Extract the decode_64bit_enabled() helper which detects
whether CPUs can run 64-bit instructions.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241026175349.84523-2-philmd@linaro.org>
-rw-r--r-- | target/mips/tcg/translate.c | 7 | ||||
-rw-r--r-- | target/mips/tcg/translate.h | 2 |
2 files changed, 8 insertions, 1 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index d92fc418ed..6c881af561 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } +bool decode_64bit_enabled(DisasContext *ctx) +{ + return ctx->hflags & MIPS_HFLAG_64; +} + /* * This code generates a "reserved instruction" exception if cpu is not * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) { gen_reserved_instruction(ctx); } } diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 5d196e69ac..ae6c25aa0c 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -217,6 +217,8 @@ void msa_translate_init(void); void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); +bool decode_64bit_enabled(DisasContext *ctx); + /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); |