diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-07 22:46:50 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 17:02:34 +0200 |
| commit | 0e045f43c45f675711c3f6836118dc7eabcc2411 (patch) | |
| tree | 120d4ec1ed2dace50ce02f9a8d8f10c6e46ec66f | |
| parent | 9e14a7b24f4cff93da664fdcfecad41fbd229e2b (diff) | |
target-tricore: add FRET instructions of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-tricore/translate.c | 19 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 2 |
2 files changed, 21 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 76bab8e5de..d4e4226f69 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3287,6 +3287,20 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_temp_free(temp); } +static void gen_fret(DisasContext *ctx) +{ + TCGv temp = tcg_temp_new(); + + tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); + tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); + tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); + tcg_gen_mov_tl(cpu_PC, temp); + tcg_gen_exit_tb(0); + ctx->bstate = BS_BRANCH; + + tcg_temp_free(temp); +} + static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { @@ -3869,6 +3883,8 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ break; + case OPC2_16_SR_FRET: + gen_fret(ctx); } } @@ -7842,6 +7858,9 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_SYS_RET: gen_compute_branch(ctx, op2, 0, 0, 0, 0); break; + case OPC2_32_SYS_FRET: + gen_fret(ctx); + break; case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(0); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index bb1939cb65..22c79f570f 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -399,6 +399,7 @@ enum { OPC2_16_SR_RET = 0x09, OPC2_16_SR_RFE = 0x08, OPC2_16_SR_DEBUG = 0x0a, + OPC2_16_SR_FRET = 0x07, }; /* OPCM_16_SR_ACCU */ enum { @@ -1438,4 +1439,5 @@ enum { OPC2_32_SYS_TRAPSV = 0x15, OPC2_32_SYS_TRAPV = 0x14, OPC2_32_SYS_RESTORE = 0x0e, + OPC2_32_SYS_FRET = 0x03, }; |