diff options
Diffstat (limited to 'system/d52/tests/test.d52')
| -rw-r--r-- | system/d52/tests/test.d52 | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/system/d52/tests/test.d52 b/system/d52/tests/test.d52 new file mode 100644 index 0000000000000..3809b2be2bbe4 --- /dev/null +++ b/system/d52/tests/test.d52 @@ -0,0 +1,102 @@ +; +; D52 V3.3.6 8052 Disassembly of test.hex +; 01/23/05 12:15 +; + org 0 +; +start: nop ; 0000 00 . + ajmp main ; 0001 01 06 .. +; + include "myfile.inc" +; + ljmp subrtn ; 0003 02 00 24 ..$ +; +main: rr a ; 0006 03 . + inc accum ; 0007 05 e0 .` ; note sfr bit def only affects indirect addressing + inc reg2 ; 0009 05 12 .. + inc @r0 ; 000b 06 . + inc @r1 ; 000c 07 . + inc r0 ; 000d 08 . + jbc abit3,loop ; 000e 10 e3 05 .c. + acall subrtn ; 0011 11 24 .$ + lcall subrtn ; 0013 12 00 24 ..$ +loop: rrc a ; 0016 13 . + dec a ; 0017 14 . + dec reg0 ; 0018 15 10 .. + dec @r0 ; 001a 16 . + dec @r1 ; 001b 17 . + dec r0 ; 001c 18 . + cjne a,#counter,loop ; 001d b4 12 f6 4.v ; do the loop + mov dptr,#vectbl ; 0020 90 00 2a ..* + jmp @a+dptr ; 0023 73 s +; +; This is a subroutine. +; +subrtn: nop ; 0024 00 . ; do nothing routine + nop ; 0025 00 . ; these nops would not be disassembled + nop ; 0026 00 . ; without the 'c' directive + nop ; 0027 00 . + nop ; 0028 00 . + ret ; 0029 22 " +; +vectbl: dw subrtn ; 002a 00 24 .$ + dw start ; 002c 00 00 .. +; +; 't' directive for ascii text +; +message: db 'This is text' ; 002e + db 0 ; 003a . +; +; Data - 'b' and 'w' directives +; + db 0 ; 003b . ; binary data + db 1,2,3 ; 003c ... +; + dw 10h ; 003f 00 10 .. ; word data + dw 20h ; 0041 00 20 . + dw 30h ; 0043 00 30 .0 +; +; +; would get junk from 45h to 48h if not for the 'i' directive +; + org 49h +; + mov r0,#five ; 0049 78 05 x. ; example of operand name 'x' directive +X004b: clr membit ; 004b c2 20 B ; 'm' bit addressable memory directive + djnz r0,X004b ; 004d d8 fc X| + ret ; 004f 22 " +; +; Register/Memory Equates +; +reg0 equ 10h +reg2 equ 12h +; +; SFR Equates +; +accum equ 0e0h +; +; SFR bit Equates +; +abit3 equ 0e3h +; +; Memory bit Equates +; +membit equ 20h +; +; Symbol equates +; +; These are symbols from the control +; file that are referenced in the code +; +counter equ 12h +; +; Operand symbol equates +; +; These are operand symbols from the control +; file that are referenced in the code +; +five equ 5 +; + end +; + |