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| author | Stephen Van Berg <stephen_van_berg@earlicker.com> | 2010-05-13 00:57:23 +0200 |
|---|---|---|
| committer | Robby Workman <rworkman@slackbuilds.org> | 2010-05-13 00:57:23 +0200 |
| commit | da95dc10a47511570a1726efa28789d94bf23a3f (patch) | |
| tree | 8e940a145d9b0d04143ce73b0aab3e593290b0c4 /academic/verilog/slack-desc | |
| parent | f334d6acba797cac07b34bcb7e016ccf2267dbba (diff) | |
academic/verilog: Added to 13.0 repository
Diffstat (limited to 'academic/verilog/slack-desc')
| -rw-r--r-- | academic/verilog/slack-desc | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/academic/verilog/slack-desc b/academic/verilog/slack-desc new file mode 100644 index 0000000000000..ae936f010a0d0 --- /dev/null +++ b/academic/verilog/slack-desc @@ -0,0 +1,19 @@ +# HOW TO EDIT THIS FILE: +# The "handy ruler" below makes it easier to edit a package description. Line +# up the first '|' above the ':' following the base package name, and the '|' on +# the right side marks the last column you can put a character in. You must make +# exactly 11 lines for the formatting to be correct. It's also customary to +# leave one space after the ':'. + + |-----handy-ruler------------------------------------------------------| +verilog: verilog (Icarus Verilog Complier) +verilog: +verilog: Icarus Verilog is a Verilog simulation and synthesis tool. It operates +verilog: as a compiler, compling source code writen in Verilog (IEEE-1364) into +verilog: some target. +verilog: +verilog: http://www.icarus.com/eda/verilog/ +verilog: +verilog: +verilog: +verilog: |