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authorAndrew Clemons <andrew.clemons@gmail.com>2022-03-12 11:38:27 +1300
committerAndrew Clemons <andrew.clemons@gmail.com>2022-03-12 12:01:20 +1300
commit63d73054e1a19eadef781078381b2fb970ef047c (patch)
tree9ef26770795bf26ec2598e136f77e89b518498af /academic/verilator
parente01495481f523d8fae3d9a3a2b69d66df71c6fac (diff)
academic/verilator: Fix slack-desc.
Signed-off-by: Andrew Clemons <andrew.clemons@gmail.com>
Diffstat (limited to 'academic/verilator')
-rw-r--r--academic/verilator/slack-desc12
1 files changed, 6 insertions, 6 deletions
diff --git a/academic/verilator/slack-desc b/academic/verilator/slack-desc
index 1bb74ecb6d0f..050595382bfe 100644
--- a/academic/verilator/slack-desc
+++ b/academic/verilator/slack-desc
@@ -8,12 +8,12 @@
|-----handy-ruler------------------------------------------------------|
verilator: verilator (the fastest free Verilog HDL simulator)
verilator:
-verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
-verilator: It "Verilates" the specified synthesizable Verilog or SystemVerilog
-verilator: code by reading it, performing lint checks, and optionally inserting
-verilator: assertion checks and coverage-analysis points. It outputs single- or
-verilator: multi-threaded .cpp and .h files, the "Verilated" code.
+verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s
+verilator: VCS. It "Verilates" the specified synthesizable Verilog or
+verilator: SystemVerilog code by reading it, performing lint checks, and
+verilator: optionally inserting assertion checks and coverage-analysis points.
+verilator: It outputs single- or verilator: multi-threaded .cpp and .h files,
+verilator: the "Verilated" code.
verilator:
verilator: homepage: https://www.veripool.org/wiki/verilator
verilator:
-verilator: