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| author | William PC <w_calandrini@hotmail.com> | 2022-10-18 20:50:48 +0700 |
|---|---|---|
| committer | Willy Sudiarto Raharjo <willysr@slackbuilds.org> | 2022-10-18 20:50:48 +0700 |
| commit | 086f66bbdb96fa1dc3c7081358b439b7889763d5 (patch) | |
| tree | bc57f1ddbd5d3061731f893778637966819cd430 /academic/DRAMsim3/slack-desc | |
| parent | 459346f491d54c6bb7c0f3718663d26cec251296 (diff) | |
academic/DRAMsim3: Added (DRAM simulator).
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
Diffstat (limited to 'academic/DRAMsim3/slack-desc')
| -rw-r--r-- | academic/DRAMsim3/slack-desc | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/academic/DRAMsim3/slack-desc b/academic/DRAMsim3/slack-desc new file mode 100644 index 0000000000000..1e16441727484 --- /dev/null +++ b/academic/DRAMsim3/slack-desc @@ -0,0 +1,19 @@ +# HOW TO EDIT THIS FILE: +# The "handy ruler" below makes it easier to edit a package description. +# Line up the first '|' above the ':' following the base package name, and +# the '|' on the right side marks the last column you can put a character in. +# You must make exactly 11 lines for the formatting to be correct. It's also +# customary to leave one space after the ':' except on otherwise blank lines. + + |-----handy-ruler------------------------------------------------------| +DRAMsim3: DRAMsim3 (DRAM simulator) +DRAMsim3: +DRAMsim3: DRAMsim3 models the timing paramaters and memory controller behavior +DRAMsim3: for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, +DRAMsim3: GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected +DRAMsim3: oriented model that includes a parameterized DRAM bank model, DRAM +DRAMsim3: controllers, command queues and system-level interfaces to interact +DRAMsim3: with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed +DRAMsim3: to be accurate, portable and parallel. +DRAMsim3: +DRAMsim3: |