1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
|
/*
* QTests for the Xilinx ZynqMP CAN controller.
*
* Copyright (c) 2020 Xilinx Inc.
*
* Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
/* Base address. */
#define CAN0_BASE_ADDR 0xFF060000
#define CAN1_BASE_ADDR 0xFF070000
/* Register addresses. */
#define R_SRR_OFFSET 0x00
#define R_MSR_OFFSET 0x04
#define R_SR_OFFSET 0x18
#define R_ISR_OFFSET 0x1C
#define R_ICR_OFFSET 0x24
#define R_TXID_OFFSET 0x30
#define R_TXDLC_OFFSET 0x34
#define R_TXDATA1_OFFSET 0x38
#define R_TXDATA2_OFFSET 0x3C
#define R_RXID_OFFSET 0x50
#define R_RXDLC_OFFSET 0x54
#define R_RXDATA1_OFFSET 0x58
#define R_RXDATA2_OFFSET 0x5C
#define R_AFR 0x60
#define R_AFMR1 0x64
#define R_AFIR1 0x68
#define R_AFMR2 0x6C
#define R_AFIR2 0x70
#define R_AFMR3 0x74
#define R_AFIR3 0x78
#define R_AFMR4 0x7C
#define R_AFIR4 0x80
/* CAN modes. */
#define CONFIG_MODE 0x00
#define NORMAL_MODE 0x00
#define LOOPBACK_MODE 0x02
#define SNOOP_MODE 0x04
#define SLEEP_MODE 0x01
#define ENABLE_CAN (1 << 1)
#define STATUS_NORMAL_MODE (1 << 3)
#define STATUS_LOOPBACK_MODE (1 << 1)
#define STATUS_SNOOP_MODE (1 << 12)
#define STATUS_SLEEP_MODE (1 << 2)
#define ISR_TXOK (1 << 1)
#define ISR_RXOK (1 << 4)
static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
uint8_t can_timestamp)
{
uint16_t size = 0;
uint8_t len = 4;
while (size < len) {
if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) {
g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
} else {
g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
}
size++;
}
}
static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
{
uint32_t int_status;
/* Read the interrupt on CAN rx. */
int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
g_assert_cmpint(int_status, ==, ISR_RXOK);
/* Read the RX register data for CAN. */
buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
/* Clear the RX interrupt. */
qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
}
static void send_data(QTestState *qts, uint64_t can_base_addr,
const uint32_t *buf_tx)
{
uint32_t int_status;
/* Write the TX register data for CAN. */
qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
/* Read the interrupt on CAN for tx. */
int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
g_assert_cmpint(int_status, ==, ISR_TXOK);
/* Clear the interrupt for tx. */
qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
}
/*
* This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
* initiate the data transfer to can-bus, CAN1 receives the data. Test compares
* the data sent from CAN0 with received on CAN1.
*/
static void test_can_bus(void)
{
const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
uint32_t status = 0;
uint8_t can_timestamp = 1;
QTestState *qts = qtest_init("-machine xlnx-zcu102"
" -object can-bus,id=canbus"
" -machine canbus0=canbus"
" -machine canbus1=canbus"
);
/* Configure the CAN0 and CAN1. */
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
/* Check here if CAN0 and CAN1 are in normal mode. */
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
send_data(qts, CAN0_BASE_ADDR, buf_tx);
read_data(qts, CAN1_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
qtest_quit(qts);
}
/*
* This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
* each CAN0 and CAN1 are compared with RX register data for respective CAN.
*/
static void test_can_loopback(void)
{
uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
uint32_t status = 0;
QTestState *qts = qtest_init("-machine xlnx-zcu102"
" -object can-bus,id=canbus"
" -machine canbus0=canbus"
" -machine canbus1=canbus"
);
/* Configure the CAN0 in loopback mode. */
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
/* Check here if CAN0 is set in loopback mode. */
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
send_data(qts, CAN0_BASE_ADDR, buf_tx);
read_data(qts, CAN0_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, 0);
/* Configure the CAN1 in loopback mode. */
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
/* Check here if CAN1 is set in loopback mode. */
status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
send_data(qts, CAN1_BASE_ADDR, buf_tx);
read_data(qts, CAN1_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, 0);
qtest_quit(qts);
}
/*
* Enable filters for CAN1. This will filter incoming messages with ID. In this
* test message will pass through filter 2.
*/
static void test_can_filter(void)
{
uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
uint32_t status = 0;
uint8_t can_timestamp = 1;
QTestState *qts = qtest_init("-machine xlnx-zcu102"
" -object can-bus,id=canbus"
" -machine canbus0=canbus"
" -machine canbus1=canbus"
);
/* Configure the CAN0 and CAN1. */
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
/* Check here if CAN0 and CAN1 are in normal mode. */
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
/* Set filter for CAN1 for incoming messages. */
qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
send_data(qts, CAN0_BASE_ADDR, buf_tx);
read_data(qts, CAN1_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
qtest_quit(qts);
}
/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
static void test_can_sleepmode(void)
{
uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
uint32_t status = 0;
uint8_t can_timestamp = 1;
QTestState *qts = qtest_init("-machine xlnx-zcu102"
" -object can-bus,id=canbus"
" -machine canbus0=canbus"
" -machine canbus1=canbus"
);
/* Configure the CAN0. */
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
/* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
send_data(qts, CAN1_BASE_ADDR, buf_tx);
/*
* Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
* Check the CAN0 status now. It should exit the sleep mode and receive the
* incoming data.
*/
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
read_data(qts, CAN0_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
qtest_quit(qts);
}
/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
static void test_can_snoopmode(void)
{
uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
uint32_t status = 0;
uint8_t can_timestamp = 1;
QTestState *qts = qtest_init("-machine xlnx-zcu102"
" -object can-bus,id=canbus"
" -machine canbus0=canbus"
" -machine canbus1=canbus"
);
/* Configure the CAN0. */
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
/* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
send_data(qts, CAN1_BASE_ADDR, buf_tx);
read_data(qts, CAN0_BASE_ADDR, buf_rx);
match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
qtest_quit(qts);
}
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
qtest_add_func("/net/can/can_bus", test_can_bus);
qtest_add_func("/net/can/can_loopback", test_can_loopback);
qtest_add_func("/net/can/can_filter", test_can_filter);
qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
return g_test_run();
}
|
