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#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program.  If not, see <http://www.gnu.org/licenses/>.

# Fields:
%rs3       27:5
%rs2       20:5
%rs1       15:5
%rd        7:5

%sh10    20:10
%csr    20:12
%rm     12:3
%nf     29:3                     !function=ex_plus_1

# immediates:
%imm_i    20:s12
%imm_s    25:s7 7:5
%imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
%imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
%imm_u    12:s20                 !function=ex_shift_12

# Argument sets:
&empty
&b    imm rs2 rs1
&i    imm rs1 rd
&j    imm rd
&r    rd rs1 rs2
&s    imm rs1 rs2
&u    imm rd
&shift     shamt rs1 rd
&atomic    aq rl rs2 rs1 rd
&rmrr      vm rd rs1 rs2
&rwdvm     vm wd rd rs1 rs2
&r2nfvm    vm rd rs1 nf
&rnfvm     vm rd rs1 rs2 nf

# Formats 32:
@r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
@i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
@b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
@u       ....................      ..... ....... &u      imm=%imm_u          %rd
@j       ....................      ..... ....... &j      imm=%imm_j          %rd

@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
@csr     ............   .....  ... ..... .......               %csr     %rs1 %rd

@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd

@r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r_nfvm  ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
@r_vm    ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
@r_vm_1  ...... . ..... ..... ... ..... .......    &rmrr vm=1 %rs2 %rs1 %rd
@r_wdvm  ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11  ..... ... ..... ....... %rs1 %rd

@hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1

@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
@sfence_vm  ....... ..... .....   ... ..... ....... %rs1


# *** Privileged Instructions ***
ecall       000000000000     00000 000 00000 1110011
ebreak      000000000001     00000 000 00000 1110011
uret        0000000    00010 00000 000 00000 1110011
sret        0001000    00010 00000 000 00000 1110011
mret        0011000    00010 00000 000 00000 1110011
wfi         0001000    00101 00000 000 00000 1110011
sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm

# *** RV32I Base Instruction Set ***
lui      ....................       ..... 0110111 @u
auipc    ....................       ..... 0010111 @u
jal      ....................       ..... 1101111 @j
jalr     ............     ..... 000 ..... 1100111 @i
beq      ....... .....    ..... 000 ..... 1100011 @b
bne      ....... .....    ..... 001 ..... 1100011 @b
blt      ....... .....    ..... 100 ..... 1100011 @b
bge      ....... .....    ..... 101 ..... 1100011 @b
bltu     ....... .....    ..... 110 ..... 1100011 @b
bgeu     ....... .....    ..... 111 ..... 1100011 @b
lb       ............     ..... 000 ..... 0000011 @i
lh       ............     ..... 001 ..... 0000011 @i
lw       ............     ..... 010 ..... 0000011 @i
lbu      ............     ..... 100 ..... 0000011 @i
lhu      ............     ..... 101 ..... 0000011 @i
sb       .......  .....   ..... 000 ..... 0100011 @s
sh       .......  .....   ..... 001 ..... 0100011 @s
sw       .......  .....   ..... 010 ..... 0100011 @s
addi     ............     ..... 000 ..... 0010011 @i
slti     ............     ..... 010 ..... 0010011 @i
sltiu    ............     ..... 011 ..... 0010011 @i
xori     ............     ..... 100 ..... 0010011 @i
ori      ............     ..... 110 ..... 0010011 @i
andi     ............     ..... 111 ..... 0010011 @i
slli     00.... ......    ..... 001 ..... 0010011 @sh
srli     00.... ......    ..... 101 ..... 0010011 @sh
srai     01.... ......    ..... 101 ..... 0010011 @sh
add      0000000 .....    ..... 000 ..... 0110011 @r
sub      0100000 .....    ..... 000 ..... 0110011 @r
sll      0000000 .....    ..... 001 ..... 0110011 @r
slt      0000000 .....    ..... 010 ..... 0110011 @r
sltu     0000000 .....    ..... 011 ..... 0110011 @r
xor      0000000 .....    ..... 100 ..... 0110011 @r
srl      0000000 .....    ..... 101 ..... 0110011 @r
sra      0100000 .....    ..... 101 ..... 0110011 @r
or       0000000 .....    ..... 110 ..... 0110011 @r
and      0000000 .....    ..... 111 ..... 0110011 @r
fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i  ---- ----   ----   ----- 001 ----- 0001111
csrrw    ............     ..... 001 ..... 1110011 @csr
csrrs    ............     ..... 010 ..... 1110011 @csr
csrrc    ............     ..... 011 ..... 1110011 @csr
csrrwi   ............     ..... 101 ..... 1110011 @csr
csrrsi   ............     ..... 110 ..... 1110011 @csr
csrrci   ............     ..... 111 ..... 1110011 @csr

# *** RV32M Standard Extension ***
mul      0000001 .....  ..... 000 ..... 0110011 @r
mulh     0000001 .....  ..... 001 ..... 0110011 @r
mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
mulhu    0000001 .....  ..... 011 ..... 0110011 @r
div      0000001 .....  ..... 100 ..... 0110011 @r
divu     0000001 .....  ..... 101 ..... 0110011 @r
rem      0000001 .....  ..... 110 ..... 0110011 @r
remu     0000001 .....  ..... 111 ..... 0110011 @r

# *** RV32A Standard Extension ***
lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st

# *** RV32F Standard Extension ***
flw        ............   ..... 010 ..... 0000111 @i
fsw        .......  ..... ..... 010 ..... 0100111 @s
fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
feq_s      1010000  ..... ..... 010 ..... 1010011 @r
flt_s      1010000  ..... ..... 001 ..... 1010011 @r
fle_s      1010000  ..... ..... 000 ..... 1010011 @r
fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2

# *** RV32D Standard Extension ***
fld        ............   ..... 011 ..... 0000111 @i
fsd        ....... .....  ..... 011 ..... 0100111 @s
fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
feq_d      1010001  ..... ..... 010 ..... 1010011 @r
flt_d      1010001  ..... ..... 001 ..... 1010011 @r
fle_d      1010001  ..... ..... 000 ..... 1010011 @r
fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm

# *** RV32H Base Instruction Set ***
hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma

# *** RV32V Extension ***

# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
vlb_v      ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlh_v      ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlw_v      ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vle_v      ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
vlbu_v     ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlhu_v     ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlwu_v     ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vlbff_v    ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v    ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v    ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vleff_v    ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v   ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v   ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v   ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vsb_v      ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
vsh_v      ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vsw_v      ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse_v      ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm

vlsb_v     ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
vlsh_v     ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
vlsw_v     ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
vlse_v     ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
vlsbu_v    ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlshu_v    ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
vlswu_v    ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
vssb_v     ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
vssh_v     ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vssw_v     ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse_v     ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm

vlxb_v     ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v     ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxw_v     ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
vlxe_v     ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
vlxbu_v    ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxhu_v    ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxwu_v    ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
# Vector ordered-indexed and unordered-indexed store insns.
vsxb_v     ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
vsxh_v     ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxw_v     ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxe_v     ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm

#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v     00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v      00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoxorw_v      00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoandw_v      01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoorw_v       01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominw_v      10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxw_v      10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominuw_v     11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxuw_v     11100 . . ..... ..... 110 ..... 0101111 @r_wdvm

# *** new major opcode OP-V ***
vadd_vv         000000 . ..... ..... 000 ..... 1010111 @r_vm
vadd_vx         000000 . ..... ..... 100 ..... 1010111 @r_vm
vadd_vi         000000 . ..... ..... 011 ..... 1010111 @r_vm
vsub_vv         000010 . ..... ..... 000 ..... 1010111 @r_vm
vsub_vx         000010 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vx        000011 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vi        000011 . ..... ..... 011 ..... 1010111 @r_vm
vwaddu_vv       110000 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_vx       110000 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_vv        110001 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_vx        110001 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_vv       110010 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_vx       110010 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_vv        110011 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_vx        110011 . ..... ..... 110 ..... 1010111 @r_vm
vwaddu_wv       110100 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_wx       110100 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_wv        110101 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_wx        110101 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_wv       110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx       110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv        110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx        110111 . ..... ..... 110 ..... 1010111 @r_vm
vadc_vvm        010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
vadc_vxm        010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
vadc_vim        010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
vmadc_vvm       010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
vmadc_vxm       010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
vmadc_vim       010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
vsbc_vvm        010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
vsbc_vxm        010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
vmsbc_vvm       010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
vmsbc_vxm       010011 1 ..... ..... 100 ..... 1010111 @r_vm_1

vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
vsetvl          1000000 ..... ..... 111 ..... 1010111  @r