blob: 52d470709c02dcee01cbfbe471d556a267aa2e54 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
|
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HEXAGON_MMVEC_H
#define HEXAGON_MMVEC_H
#define MAX_VEC_SIZE_LOGBYTES 7
#define MAX_VEC_SIZE_BYTES (1 << MAX_VEC_SIZE_LOGBYTES)
#define NUM_VREGS 32
#define NUM_QREGS 4
typedef uint32_t VRegMask; /* at least NUM_VREGS bits */
typedef uint32_t QRegMask; /* at least NUM_QREGS bits */
#define VECTOR_SIZE_BYTE (fVECSIZE())
typedef union {
uint64_t ud[MAX_VEC_SIZE_BYTES / 8];
int64_t d[MAX_VEC_SIZE_BYTES / 8];
uint32_t uw[MAX_VEC_SIZE_BYTES / 4];
int32_t w[MAX_VEC_SIZE_BYTES / 4];
uint16_t uh[MAX_VEC_SIZE_BYTES / 2];
int16_t h[MAX_VEC_SIZE_BYTES / 2];
uint8_t ub[MAX_VEC_SIZE_BYTES / 1];
int8_t b[MAX_VEC_SIZE_BYTES / 1];
} MMVector;
typedef union {
uint64_t ud[2 * MAX_VEC_SIZE_BYTES / 8];
int64_t d[2 * MAX_VEC_SIZE_BYTES / 8];
uint32_t uw[2 * MAX_VEC_SIZE_BYTES / 4];
int32_t w[2 * MAX_VEC_SIZE_BYTES / 4];
uint16_t uh[2 * MAX_VEC_SIZE_BYTES / 2];
int16_t h[2 * MAX_VEC_SIZE_BYTES / 2];
uint8_t ub[2 * MAX_VEC_SIZE_BYTES / 1];
int8_t b[2 * MAX_VEC_SIZE_BYTES / 1];
MMVector v[2];
} MMVectorPair;
typedef union {
uint64_t ud[MAX_VEC_SIZE_BYTES / 8 / 8];
int64_t d[MAX_VEC_SIZE_BYTES / 8 / 8];
uint32_t uw[MAX_VEC_SIZE_BYTES / 4 / 8];
int32_t w[MAX_VEC_SIZE_BYTES / 4 / 8];
uint16_t uh[MAX_VEC_SIZE_BYTES / 2 / 8];
int16_t h[MAX_VEC_SIZE_BYTES / 2 / 8];
uint8_t ub[MAX_VEC_SIZE_BYTES / 1 / 8];
int8_t b[MAX_VEC_SIZE_BYTES / 1 / 8];
} MMQReg;
typedef struct {
MMVector data;
DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES);
target_ulong va[MAX_VEC_SIZE_BYTES];
bool op;
int op_size;
} VTCMStoreLog;
/* Types of vector register assignment */
typedef enum {
EXT_DFL, /* Default */
EXT_NEW, /* New - value used in the same packet */
EXT_TMP /* Temp - value used but not stored to register */
} VRegWriteType;
#endif
|
