aboutsummaryrefslogtreecommitdiff
path: root/target/cris/cpu.c
blob: 9222717f3e541e5192f8ada514326efcb7e68749 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
/*
 * QEMU CRIS CPU
 *
 * Copyright (c) 2008 AXIS Communications AB
 * Written by Edgar E. Iglesias.
 *
 * Copyright (c) 2012 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see
 * <http://www.gnu.org/licenses/lgpl-2.1.html>
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
#include "mmu.h"


static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
    CRISCPU *cpu = CRIS_CPU(cs);

    cpu->env.pc = value;
}

static bool cris_cpu_has_work(CPUState *cs)
{
    return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}

static void cris_cpu_reset(DeviceState *dev)
{
    CPUState *s = CPU(dev);
    CRISCPU *cpu = CRIS_CPU(s);
    CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
    CPUCRISState *env = &cpu->env;
    uint32_t vr;

    ccc->parent_reset(dev);

    vr = env->pregs[PR_VR];
    memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
    env->pregs[PR_VR] = vr;

#if defined(CONFIG_USER_ONLY)
    /* start in user mode with interrupts enabled.  */
    env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
#else
    cris_mmu_init(env);
    env->pregs[PR_CCS] = 0;
#endif
}

static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
{
    ObjectClass *oc;
    char *typename;

#if defined(CONFIG_USER_ONLY)
    if (strcasecmp(cpu_model, "any") == 0) {
        return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
    }
#endif

    typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model);
    oc = object_class_by_name(typename);
    g_free(typename);
    if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
                       object_class_is_abstract(oc))) {
        oc = NULL;
    }
    return oc;
}

/* Sort alphabetically by VR. */
static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
{
    CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
    CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);

    /*  */
    if (ccc_a->vr > ccc_b->vr) {
        return 1;
    } else if (ccc_a->vr < ccc_b->vr) {
        return -1;
    } else {
        return 0;
    }
}

static void cris_cpu_list_entry(gpointer data, gpointer user_data)
{
    ObjectClass *oc = data;
    const char *typename = object_class_get_name(oc);
    char *name;

    name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX));
    qemu_printf("  %s\n", name);
    g_free(name);
}

void cris_cpu_list(void)
{
    GSList *list;

    list = object_class_get_list(TYPE_CRIS_CPU, false);
    list = g_slist_sort(list, cris_cpu_list_compare);
    qemu_printf("Available CPUs:\n");
    g_slist_foreach(list, cris_cpu_list_entry, NULL);
    g_slist_free(list);
}

static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
{
    CPUState *cs = CPU(dev);
    CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
    Error *local_err = NULL;

    cpu_exec_realizefn(cs, &local_err);
    if (local_err != NULL) {
        error_propagate(errp, local_err);
        return;
    }

    cpu_reset(cs);
    qemu_init_vcpu(cs);

    ccc->parent_realize(dev, errp);
}

#ifndef CONFIG_USER_ONLY
static void cris_cpu_set_irq(void *opaque, int irq, int level)
{
    CRISCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;

    if (irq == CRIS_CPU_IRQ) {
        /*
         * The PIC passes us the vector for the IRQ as the value it sends
         * over the qemu_irq line
         */
        cpu->env.interrupt_vector = level;
    }

    if (level) {
        cpu_interrupt(cs, type);
    } else {
        cpu_reset_interrupt(cs, type);
    }
}
#endif

static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
{
    CRISCPU *cc = CRIS_CPU(cpu);
    CPUCRISState *env = &cc->env;

    if (env->pregs[PR_VR] != 32) {
        info->mach = bfd_mach_cris_v0_v10;
        info->print_insn = print_insn_crisv10;
    } else {
        info->mach = bfd_mach_cris_v32;
        info->print_insn = print_insn_crisv32;
    }
}

static void cris_cpu_initfn(Object *obj)
{
    CRISCPU *cpu = CRIS_CPU(obj);
    CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
    CPUCRISState *env = &cpu->env;

    cpu_set_cpustate_pointers(cpu);

    env->pregs[PR_VR] = ccc->vr;

#ifndef CONFIG_USER_ONLY
    /* IRQ and NMI lines.  */
    qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
#endif
}

static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 8;
    cc->do_interrupt = crisv10_cpu_do_interrupt;
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;
    cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}

static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 9;
    cc->do_interrupt = crisv10_cpu_do_interrupt;
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;
    cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}

static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 10;
    cc->do_interrupt = crisv10_cpu_do_interrupt;
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;
    cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}

static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 11;
    cc->do_interrupt = crisv10_cpu_do_interrupt;
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;
    cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}

static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 17;
    cc->do_interrupt = crisv10_cpu_do_interrupt;
    cc->gdb_read_register = crisv10_cpu_gdb_read_register;
    cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}

static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
{
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    ccc->vr = 32;
}

static void cris_cpu_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    CPUClass *cc = CPU_CLASS(oc);
    CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);

    device_class_set_parent_realize(dc, cris_cpu_realizefn,
                                    &ccc->parent_realize);

    device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset);

    cc->class_by_name = cris_cpu_class_by_name;
    cc->has_work = cris_cpu_has_work;
    cc->do_interrupt = cris_cpu_do_interrupt;
    cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
    cc->dump_state = cris_cpu_dump_state;
    cc->set_pc = cris_cpu_set_pc;
    cc->gdb_read_register = cris_cpu_gdb_read_register;
    cc->gdb_write_register = cris_cpu_gdb_write_register;
    cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
    cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
    dc->vmsd = &vmstate_cris_cpu;
#endif

    cc->gdb_num_core_regs = 49;
    cc->gdb_stop_before_watchpoint = true;

    cc->disas_set_info = cris_disas_set_info;
    cc->tcg_ops.initialize = cris_initialize_tcg;
}

#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
     {                                          \
         .parent = TYPE_CRIS_CPU,               \
         .class_init = initfn,                  \
         .name = CRIS_CPU_TYPE_NAME(cpu_model), \
     }

static const TypeInfo cris_cpu_model_type_infos[] = {
    {
        .name = TYPE_CRIS_CPU,
        .parent = TYPE_CPU,
        .instance_size = sizeof(CRISCPU),
        .instance_init = cris_cpu_initfn,
        .abstract = true,
        .class_size = sizeof(CRISCPUClass),
        .class_init = cris_cpu_class_init,
    },
    DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init),
    DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init),
    DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init),
    DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init),
    DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init),
    DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init),
};

DEFINE_TYPES(cris_cpu_model_type_infos)