blob: 9be1fd80ed8bdd6827f7fad409927096627d3b10 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
/*
* QEMU RISC-V Hart Array interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* Holds the state of a heterogenous array of RISC-V harts
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_RISCV_HART_H
#define HW_RISCV_HART_H
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "qom/object.h"
#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
typedef struct RISCVHartArrayState RISCVHartArrayState;
DECLARE_INSTANCE_CHECKER(RISCVHartArrayState, RISCV_HART_ARRAY,
TYPE_RISCV_HART_ARRAY)
struct RISCVHartArrayState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t num_harts;
uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
};
#endif
|
