1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
/*
* QEMU PowerPC PowerNV LPC controller
*
* Copyright (c) 2016, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _PPC_PNV_LPC_H
#define _PPC_PNV_LPC_H
#include "hw/ppc/pnv_psi.h"
#define TYPE_PNV_LPC "pnv-lpc"
#define PNV_LPC(obj) \
OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
#define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
#define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC)
typedef struct PnvLpcController {
DeviceState parent;
uint64_t eccb_stat_reg;
uint32_t eccb_data_reg;
/* OPB bus */
MemoryRegion opb_mr;
AddressSpace opb_as;
/* ISA IO and Memory space */
MemoryRegion isa_io;
MemoryRegion isa_mem;
MemoryRegion isa_fw;
/* Windows from OPB to ISA (aliases) */
MemoryRegion opb_isa_io;
MemoryRegion opb_isa_mem;
MemoryRegion opb_isa_fw;
/* Registers */
MemoryRegion lpc_hc_regs;
MemoryRegion opb_master_regs;
/* OPB Master LS registers */
uint32_t opb_irq_stat;
uint32_t opb_irq_mask;
uint32_t opb_irq_pol;
uint32_t opb_irq_input;
/* LPC HC registers */
uint32_t lpc_hc_fw_seg_idsel;
uint32_t lpc_hc_fw_rd_acc_size;
uint32_t lpc_hc_irqser_ctrl;
uint32_t lpc_hc_irqmask;
uint32_t lpc_hc_irqstat;
uint32_t lpc_hc_error_addr;
/* XSCOM registers */
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
PnvPsi *psi;
} PnvLpcController;
#define PNV_LPC_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvLpcClass, (klass), TYPE_PNV_LPC)
#define PNV_LPC_GET_CLASS(obj) \
OBJECT_GET_CLASS(PnvLpcClass, (obj), TYPE_PNV_LPC)
typedef struct PnvLpcClass {
DeviceClass parent_class;
int psi_irq;
DeviceRealize parent_realize;
} PnvLpcClass;
ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
#endif /* _PPC_PNV_LPC_H */
|
