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2023-11-14Merge tag 'misc-fixes-20231113' of https://github.com/philmd/qemu into stagingStefan Hajnoczi
Misc fixes for 8.2 - Missing Kconfig dependency in hw/mips (Marc-André) - Typo in VMWare model (Alexandra) - New avocado test for x86 processors addressing (Ani) - Fix SyntaxWarnings in avocado (Thomas) - Update virtio-fs mailing list address in MAINTAINERS (Stefan) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVSaAwACgkQ4+MsLN6t # wN7L9RAAvlX5MKJe6d3+gYV8NciEYFQGWzgSjtc0IzRenYf1wvxXubFnmeTJ3kfF # VOugAmeQUx5xvD0iPNrYCFn5fb1ZIFDuES25TsUSN38GCfo1/1+pG+wBWPJRwnQg # LhRHLSzwJOiUSzOEWrVW/4f2TUM1svUM7WKAWB1AbO2Dd3BKzb25/AEdgYWCeQKV # xrBFUH/owNCnWHxIFfLEO8Gt2WGkCLgblvLpeu5Mzds/5JcAi1Fb9lgpvvYxB1Jk # Jgb2ic4Lp6+aTxYxS/+EbQcZciM1M7XXVN57xsQZEcave5CQ9fN8dMbTy3GJxEfJ # OqWzLbwxybQCDA2f2Kd0HEv+U828ZD6/8HDfFk1JmZjE8UJ9vsvdnhQDDJOn5VJu # INyupPsgaG86jaQavzAQJ7Cehe4SdEX0B11mdPfujooy4FvO79O8AzlMM2YG8ARn # YydUzc1RnzE9l67RuEPvqiw1htpjJwV32v7nNZzsoBpqHG5OXAAD732OYnu/30a0 # U73tApRwPDUX3kiS8kUvXLq4/2NxFbX5VDx1bcJPTsweGplr59tPzMRpRxKQGhwa # WEsjjqnDNEjYVzTMVfFRQlvDUkcr5Rrgd51Q3MDbm6inCf2JofT4m7UmvFVmOW3p # w7IAbiguwyxC+Us9AkPTh03FYlzT2B+3XhKbAxcYJZ5/oH1O3x8= # =SFhl # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 13:16:44 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-fixes-20231113' of https://github.com/philmd/qemu: MAINTAINERS: update virtio-fs mailing list address tests/avocado/machine_s390_ccw_virtio.py: Fix SyntaxWarnings from python 3.12 tests/avocado: add test to exercise processor address space memory bound checks hw/display/vmware_vga: fix probably typo hw/mips: LOONGSON3V depends on UNIMP device Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-13tests/avocado/machine_s390_ccw_virtio.py: Fix SyntaxWarnings from python 3.12Thomas Huth
Python 3.12 now warns about backslashes in strings that aren't used for escaping a special character from Python. Silence the warning by using raw strings here instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231113140721.46903-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-13tests/avocado: add test to exercise processor address space memory bound checksAni Sinha
QEMU has validations to make sure that a VM is not started with more memory (static and hotpluggable memory) than what the guest processor can address directly with its addressing bits. This change adds a test to make sure QEMU fails to start with a specific error message when an attempt is made to start a VM with more memory than what the processor can directly address. The test also checks for passing cases when the address space of the processor is capable of addressing all memory. Boundary cases are tested. CC: imammedo@redhat.com CC: David Hildenbrand <david@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-ID: <20231109045601.33349-1-anisinha@redhat.com> Message-ID: <D5D8D419-76BA-4FB0-9BAC-4F7470A052FC@redhat.com> [PMD: Use SPDX tag] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-13Merge tag 'pull-request-2023-11-13' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Fix compilation with Clang 17 on s390x hosts * Two small s390x PCI fixes * Update MAINTAINERS file with more entries * Fix NetBSD VM test * Clean up some bad wordings # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVSAoIRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVXBg//VVZS5CXEfOFV91I1kqQnLCvgwmuAyqEg # PI2/HBxuhzeBx+F1t7uR0n15tUPi1zkFFBOpyBDBubvWcp4vGvFwLQoiBCUvNzBA # +b1vMySP+K0OO1X5yT3cFHXF9q0o0V5WADwemf5RglIPjlTOIiz9qhD4EYqd2QHC # EUd9Y45DP4Y0V5raHLjY990f/zr3PuSAB6MASFTUnKdgGkRqonLWdLDdIZNDrZuL # oGwx1ALXgBOMV3yNyQx9jZBT24git/ai1vd9AU/d3JRKDPsd+4vC39+PTI9NH4h6 # oQglvo399f64cir1f1JJ3MN4ZtwXZpwUkjeTMcR9XZxk7GibU7P2arG5M3TERdmE # VLqylYsnbJojWOeCH+TViJapRhg1CzUveVlQofr7GHvf2N3oy3BrKaV715gauEyW # zpjbhSPpIQu9WFXt8+tSquqbvpAP/VlLrOV73D4LzJ7WdTa9CHmSek8D0zoRQDZR # 8OixrgoBKS+pmBDmTve5gFsIKhZIz9CrmaAKKYdskC8blENxCng8LOFp7sg2PK3M # U0lWYoDS7qZ85761Bl+QaBdFocdahQqkO/LUQuhoSt2OvA1EGAz2FdVSKkmPDdSS # P/homr4hOXIqJFSsZj0YNUTIXsXwLBvKjvcJPAWYgbXZhim0LtPQTQO3+ignwGyu # RXjaVkvkf/s= # =+2rp # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Nov 2023 06:03:30 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-11-13' of https://gitlab.com/thuth/qemu: hw/audio/es1370: Clean up comment tests/tsan: Rename the file with the entries that should be ignored test-resv-mem: Fix CID 1523911 tests/vm/netbsd: Use Python v3.11 MAINTAINERS: Add a general architecture section for x86 MAINTAINERS: Extend the Stellaris section MAINTAINERS: Add hw/display/sii9022.c to the Versatile Express section MAINTAINERS: Add hw/input/ads7846.c to the PXA2XX section MAINTAINERS: Add include/hw/input/pl050.h to the PrimeCell/CMSDK section s390x/pci: only limit DMA aperture if vfio DMA limit reported s390x/pci: bypass vfio DMA counting when using cdev host/include/generic/host/atomic128: Fix compilation problem with Clang 17 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-13tests/tsan: Rename the file with the entries that should be ignoredThomas Huth
Let's use a better file name here. Message-ID: <20231109174720.375873-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13test-resv-mem: Fix CID 1523911Eric Auger
Coverity complains about passing "&expected" to "run_range_inverse_array", which dereferences null "expected". I guess the problem is that the compare_ranges() loop dereferences 'e' without testing it. However the loop condition is based on 'ranges' which is garanteed to have the same length as 'expected' given the g_assert_cmpint() just before the loop. So the code looks safe to me. Nevertheless adding a test on expected before the loop to get rid of the warning. Fixes: CID 1523901 Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: Coverity (CID 1523901) Message-ID: <20231110083654.277345-1-eric.auger@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13tests/vm/netbsd: Use Python v3.11Philippe Mathieu-Daudé
We requiere the 'ninja-build', which depends on 'python311': $ pkgin show-deps ninja-build direct dependencies for ninja-build-1.11.1nb1 python311>=3.11.0 So we end up installing both Python v3.10 and v3.11: [31/76] installing python311-3.11.5... [54/76] installing python310-3.10.13... [74/76] installing py310-expat-3.10.13nb1... Then the build system picks Python v3.11, and doesn't find py-expat because we only installed the 3.10 version: python determined to be '/usr/pkg/bin/python3.11' python version: Python 3.11.5 *** Ouch! *** Python's pyexpat module is not found. It's normally part of the Python standard library, maybe your distribution packages it separately? Either install pyexpat, or alleviate the need for it in the first place by installing pip and setuptools for '/usr/pkg/bin/python3.11'. (Hint: NetBSD's pkgsrc debundles this to e.g. 'py310-expat'.) ERROR: python venv creation failed Fix by installing py-expat for v3.11. Remove the v3.10 packages since we aren't using them anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231109150900.91186-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-13tests/qapi-schema: Tidy up pylint warnings and adviceMarkus Armbruster
Pylint warns: tests/qapi-schema/test-qapi.py:139:13: W1514: Using open without explicitly specifying an encoding (unspecified-encoding) tests/qapi-schema/test-qapi.py:143:13: W1514: Using open without explicitly specifying an encoding (unspecified-encoding) Add encoding='utf-8'. Pylint advises: tests/qapi-schema/test-qapi.py:143:13: R1732: Consider using 'with' for resource-allocating operations (consider-using-with) Silence this by returning the value directly. Pylint advises: tests/qapi-schema/test-qapi.py:221:4: R1722: Consider using sys.exit() (consider-using-sys-exit) tests/qapi-schema/test-qapi.py:226:4: R1722: Consider using sys.exit() (consider-using-sys-exit) Sure, why not. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20231025092925.1785934-1-armbru@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>
2023-11-09Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingStefan Hajnoczi
Block layer patches - Graph locking part 6 (bs->file/backing) - ahci: trigger either error IRQ or regular IRQ, not both # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmVLvccRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9ZkFg//awQoPiGnYzHpqcx2tGCM2AqBV+mFkbZr # BKI5vp8FYfJtgMuHjC8jabL24NRMPpT+HbCzoxwjJU+nnnr85qr7R5iGwG6kfgX6 # HJlAXYXdY6e7l+FV44PBJ52vOoGCsh1GHg8HlKsHMaxSdXi9C1axHJ6rCAjnWXE0 # FQ4znCBVs/9HiKsvu4Wdm5muX2ShftFRM/toAwA+fLEOealX8WEXoRFJXI40bYbR # OR7aJXWMDQrljlqdKk2FXvK337/tpofXmXf3NIE1R2pmY4x5Fg8bfChZn4UaaCdN # n+0AhmE4ScI0rXuaXXYOvTO9vdTzXeBROG6tX03t9rrQfB6wPcGVeXRo/uusslAW # sDH8NLz7uHFOooV02Fs8CKDdVrNNw5qjziclSGa0Po7vqOV1TKI8OTiNpsDLmdI5 # +DQvC6N+IU1pSOXImATSHkheGWggsegrsgN6PdrlzHEXJwWoAaRD0T06MRn74/pL # gCegK2ez4RJYsci7C5b0gaqY/QBsMj8EUfEGVHvVyuVSoPRwiq4ehPqSQ+siA3xP # KxYR0e4+QIfRmxqCzaJhiQ3DDGdt8UcO3yF0XcKXEqWwgFAGQKNeUG314jginvmA # iaJzC0dHbiGcagAk7Ey8iyzfxQDWM6ixzJtGv7VLILepzCuu8vaJXy5qeEtTM/ZI # EXoDGceNSvw= # =ikBW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 09 Nov 2023 00:56:39 HKT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: (25 commits) hw/ide/ahci: trigger either error IRQ or regular IRQ, not both block: Protect bs->file with graph_lock block: Take graph lock for most of .bdrv_open vhdx: Take locks for accessing bs->file qcow2: Take locks for accessing bs->file block: Add missing GRAPH_RDLOCK annotations block: Introduce bdrv_co_change_backing_file() blkverify: Add locking for request_fn block: Protect bs->backing with graph_lock block: Mark bdrv_replace_node() GRAPH_WRLOCK block: Mark bdrv_replace_node_common() GRAPH_WRLOCK block: Inline bdrv_set_backing_noperm() block: Mark bdrv_set_backing_hd_drained() GRAPH_WRLOCK block: Mark bdrv_cow_child() and callers GRAPH_RDLOCK block: Mark bdrv_filter_child() and callers GRAPH_RDLOCK block: Mark bdrv_chain_contains() and callers GRAPH_RDLOCK block: Mark bdrv_(un)freeze_backing_chain() and callers GRAPH_RDLOCK block: Mark bdrv_skip_filters() and callers GRAPH_RDLOCK block: Mark bdrv_skip_implicit_filters() and callers GRAPH_RDLOCK block: Mark bdrv_filter_or_cow_bs() and callers GRAPH_RDLOCK ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08block: Introduce bdrv_co_change_backing_file()Kevin Wolf
bdrv_change_backing_file() is called both inside and outside coroutine context. This makes it difficult for it to take the graph lock internally. It also means that driver implementations need to be able to run outside of coroutines, too. Switch it to the usual model with a coroutine based implementation and a co_wrapper instead. The new function is marked GRAPH_RDLOCK. As the co_wrapper now runs the function in the AioContext of the node (as it should always have done), this is not GLOBAL_STATE_CODE() any more. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231027155333.420094-20-kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-08block: Protect bs->backing with graph_lockKevin Wolf
Almost all functions that access bs->backing already take the graph lock now. Add locking to the remaining users and finally annotate the struct field itself as protected by the graph lock. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231027155333.420094-18-kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-08Revert "tests/tcg/nios2: Re-enable linux-user tests"Alex Bennée
nios2 signal tests are broken again: retry.py -n 10 -c -- ./qemu-nios2 ./tests/tcg/nios2-linux-user/signals Results summary: 0: 8 times (80.00%), avg time 2.254 (0.00 varience/0.00 deviation) -11: 2 times (20.00%), avg time 0.253 (0.00 varience/0.00 deviation) Ran command 10 times, 8 passes This wasn't picked up by CI as we don't have a docker container that can build QEMU with the nios2 compiler. I don't have time to bisect the breakage and the target is orphaned anyway so take the easy route and revert it. This reverts commit 20e7524ff9f0cab4c9a0306014d6f3d7b467ae1e. Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-23-alex.bennee@linaro.org>
2023-11-08plugins: make test/example plugins work on windowsGreg Manning
Generate a qemu_plugin_api.lib delay import lib on windows, for windows qemu plugins to link against. Implement an example dll load fail hook to link up the API functions correctly when a plugin is loaded on windows. Update the build scripts for the test and example plugins to use these things. Signed-off-by: Greg Manning <gmanning@rapitasystems.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231102172053.17692-3-gmanning@rapitasystems.com> [AJB: use find_program for dlltool, s/Windows/windows/] Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-15-alex.bennee@linaro.org>
2023-11-08tests/avocado: update the tcg_plugins testAlex Bennée
There are a number of things that are broken on the test currently so lets fix that up: - replace retired Debian kernel for tuxrun_baseline one - remove "detected repeat instructions test" since ea185a55 - log total counted instructions/memory accesses Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-8-alex.bennee@linaro.org>
2023-11-08tests/tcg: add an explicit gdbstub register testerAlex Bennée
We already do a couple of "info registers" for specific tests but this is a more comprehensive multiarch test. It also has some output helpful for debugging the gdbstub by showing which XML features are advertised and what the underlying register numbers are. My initial motivation was to see if there are any duplicate register names exposed via the gdbstub while I was reviewing the proposed register interface for TCG plugins. Mismatches between the xml and remote-desc are reported for debugging but do not fail the test. We also skip the tests for the following arches for now until we can investigate and fix any issues: - s390x (fails to read v0l->v15l, not seen in remote-registers) - ppc64 (fails to read vs0h->vs31h, not seen in remote-registers) Cc: Akihiko Odaki <akihiko.odaki@daynix.com> Cc: Luis Machado <luis.machado@linaro.org> Cc: Ilya Leoshkevich <iii@linux.ibm.com> Cc: qemu-s390x@nongnu.org Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: qemu-ppc@nongnu.org Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-7-alex.bennee@linaro.org>
2023-11-08Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into stagingStefan Hajnoczi
ppc patch queue for 2023-11-07: This queue, the last one before the 8.2 feature freeze, has miscellanous changes that includes new PowerNV features and the new AmigaONE XE board. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZUqiORYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFkBSUA/2qm8CyrRqY5+tsjtWQqZmPZ3L1F # CgnXFNqtY2tzbTe5AQCi6FeQBEmXbZYVfryZyA+CQ4DUERc+18pe6hV3bBR9Cg== # =cnHS # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu: ppc: qtest already exports qtest_rtas_call() hw/pci-host: Update PHB5 XSCOM registers ppc/pnv: Fix number of I2C engines and ports for power9/10 ppc/pnv: Connect PNV I2C controller to powernv10 ppc/pnv: Connect I2C controller model to powernv9 chip ppc/pnv: Add an I2C controller model tests/avocado: Add test for amigaone board hw/ppc: Add emulation of AmigaOne XE board hw/pci-host: Add emulation of Mai Logic Articia S Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08Merge tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi
staging * Fix s390x CPU reconfiguration information in the SCLP facility map * Fix condition code problem in the CLC and LAALG instruction * Fix ordering of the new s390x topology list entries * Add some more files to the MAINTAINERS file * Allow newer versions of Tesseract in the m68k nextcube test # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmVKgksRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWIHg//TM3JOpsMEqHKlUKqOJH02mFQrK6H7LG0 # BC56FG7T+/mpYs1NTG92t8nCK03C2ZCweQWD7ZulRJAjPhZv+TF5bJEForivU7+k # PKEshz9xKCWn2YGyNnf2LA06J1JkF215+KlReOoxwSgj1cPlHfBLQ0DtxmpJJZ1G # h5p4d26BbSlwR58HrFWTlhgJMPenl59BETUGIK1FklBxunmZeeijddfniAhOT44y # i0u9/H9KCg3tkwBROUy+42QV+ef32kz/yvi5RmYQI5W7PixO4sxH6MYduOjshsu9 # wK70f8EOwiZV6lFxqmbV7vxFeNnp5IuaVU7PMBoAkwZqLw99mSFy1+1BabCuL5b+ # 3iUTiD4UW48MYwE2Ua6Lit4kpfjhwcp/UYz6pIk6TCBQX6LfzO+nj+rod0GdIpyZ # 4Lwm7jBtpTlYkGrsMvpA/qcidOtqPA1lmBTNlY1hFodQF6KWtyObn0w5AM80xeeU # /mGxQDz97Bpz7LKZvhu+k38jaWvnJFnl3jF1zet88CYL9YL+YI/k1KjhFafCXb0V # 38Xpt5JTWxyLSh2B3gx0OpokX5bftvW9GlLix0HqL7c23uYwR2Bq+Rd6I8SAlk4C # uJq6gqP8IFBFHfgbmyqf/fyd/eHxm7J1voIdy9PZyxZ1JYT9A7yu56qV6SJYwCpr # aARwui/Dm4o= # =y+cC # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Nov 2023 02:30:35 HKT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu: target/s390x/cpu topology: Fix ordering and creation of TLEs tests/tcg/s390x: Test ADD LOGICAL WITH CARRY tests/tcg/s390x: Test LAALG with negative cc_src target/s390x: Fix LAALG not updating cc_src tests/tcg/s390x: Test CLC with inaccessible second operand target/s390x: Fix CLC corrupting cc_src target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block() s390/sclp: fix SCLP facility map tests/avocado: Allow newer versions of tesseract in the nextcube test MAINTAINERS: Add artist.c to the hppa machine section MAINTAINERS: Add the virtio-gpu documentation to the corresponding section Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-08Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into stagingStefan Hajnoczi
Misc hardware patch queue HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe) Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu) Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang) QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe) UI: - Use correct key names in titles on MacOS / SDL2 (Adrian) MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe) Nios2: - Create IRQs *after* vCPU is realized (Philippe) PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe) S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe) X86: - HVF & KVM cleanups (Philippe) Various targets: - Use env_archcpu() to optimize (Philippe) Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07tests/avocado: Add test for amigaone boardBALATON Zoltan
Add an avocado test for the amigaone board that tests it with the firmware. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <b1a0246840fcff1fe6bbd8685e2474a9231b34c5.1698406922.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-11-07tests/tcg/s390x: Test ADD LOGICAL WITH CARRYIlya Leoshkevich
Add a test that tries different combinations of ADD LOGICAL WITH CARRY instructions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20231106093605.1349201-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-07tests/tcg/s390x: Test LAALG with negative cc_srcIlya Leoshkevich
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231106093605.1349201-5-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-07tests/tcg/s390x: Test CLC with inaccessible second operandIlya Leoshkevich
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231106093605.1349201-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-07tests/avocado: Allow newer versions of tesseract in the nextcube testThomas Huth
Current Linux distros ship version 5 of the tesseract OCR software, so the nextcube screen test is ignored there. Let's make the check more flexible to allow newer versions, too, and remove the old v3 test since most Linux distros don't ship this version anymore. Message-ID: <20231101204323.35533-1-huth@tuxfamily.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2023-11-07block: Mark bdrv_replace_node() GRAPH_WRLOCKKevin Wolf
Instead of taking the writer lock internally, require callers to already hold it when calling bdrv_replace_node(). Its callers may already want to hold the graph lock and so wouldn't be able to call functions that take it internally. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231027155333.420094-17-kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-07block: Mark block_job_add_bdrv() GRAPH_WRLOCKKevin Wolf
Instead of taking the writer lock internally, require callers to already hold it when calling block_job_add_bdrv(). These callers will typically already hold the graph lock once the locking work is completed, which means that they can't call functions that take it internally. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20231027155333.420094-6-kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-11-07hw/i2c: pmbus: reset page register for out of range readsTitus Rwantare
The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages. Reviewed-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07tests/qtest: add tests for ADM1266Titus Rwantare
The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07tests/qtest: ahci-test: add test exposing reset issue with pending callbackFiona Ebner
Before commit "hw/ide: reset: cancel async DMA operation before resetting state", this test would fail, because a reset with a pending write operation would lead to an unsolicited write to the first sector of the disk. The test writes a pattern to the beginning of the disk and verifies that it is still intact after a reset with a pending operation. It also checks that the pending operation actually completes correctly. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com> Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07tests/unit: Rename test-x86-cpuid.c to test-x86-topo.cZhao Liu
The tests in this file actually test the APIC ID combinations. Rename to test-x86-topo.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Babu Moger <babu.moger@amd.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231024090323.1859210-3-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07tests/unit/test-seccomp: Remove mentions of softmmu in test namesPhilippe Mathieu-Daudé
Wether we are using a software MMU or not is irrelevant for the seccomp facility. The facility is restricted to system emulation, but such detail isn't really helpful, so directly drop the 'softmmu' mention from the test names. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231002145104.52193-3-philmd@linaro.org>
2023-11-07tests/vm/ubuntu.aarch64: Correct comment about TCG specific delayPhilippe Mathieu-Daudé
Wether we use a software MMU or not to set the SSH timeout isn't really relevant. What we want to know is if we use a hardware or software accelerator (TCG). Replace the 'softmmu' mention by 'TCG'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231002145104.52193-2-philmd@linaro.org>
2023-11-07Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi
into staging virtio,pc,pci: features, fixes virtio sound card support vhost-user: back-end state migration cxl: line length reduction enabling fabric management vhost-vdpa: shadow virtqueue hash calculation Support shadow virtqueue RSS Support tests: CPU topology related smbios test cases Fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmVKDDoPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpF08H/0Zts8uvkHbgiOEJw4JMHU6/VaCipfIYsp01 # GSfwYOyEsXJ7GIxKWaCiMnWXEm7tebNCPKf3DoUtcAojQj3vuF9XbWBKw/bfRn83 # nGO/iiwbYViSKxkwqUI+Up5YiN9o0M8gBFrY0kScPezbnYmo5u2bcADdEEq6gH68 # D0Ea8i+WmszL891ypvgCDBL2ObDk3qX3vA5Q6J2I+HKX2ofJM59BwaKwS5ghw+IG # BmbKXUZJNjUQfN9dQ7vJuiuqdknJ2xUzwW2Vn612ffarbOZB1DZ6ruWlrHty5TjX # 0w4IXEJPBgZYbX9oc6zvTQnbLDBJbDU89mnme0TcmNMKWmQKTtc= # =vEv+ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 18:06:50 HKT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (63 commits) acpi/tests/avocado/bits: enable console logging from bits VM acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point hw/cxl: Add tunneled command support to mailbox for switch cci. hw/cxl: Add dummy security state get hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions hw/cxl/mbox: Add Get Background Operation Status Command hw/cxl: Add support for device sanitation hw/cxl/mbox: Wire up interrupts for background completion hw/cxl/mbox: Add support for background operations hw/cxl: Implement Physical Ports status retrieval hw/pci-bridge/cxl_downstream: Set default link width and link speed hw/cxl/mbox: Add Physical Switch Identify command. hw/cxl/mbox: Add Information and Status / Identify command hw/cxl: Add a switch mailbox CCI function hw/pci-bridge/cxl_upstream: Move defintion of device to header. hw/cxl/mbox: Generalize the CCI command processing hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState hw/cxl/mbox: Split mailbox command payload into separate input and output hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue. ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07acpi/tests/avocado/bits: enable console logging from bits VMAni Sinha
Console logs from the VM can be useful for debugging when things go wrong. Other avocado tests enables them. This change enables console logging with the following changes: - point to the newer bios bits image that actually enabled VM console. - change the bits test to drain the console logs from the VM and write the logs. - wait for SHUTDOWN event from QEMU so that console logs can be drained out of the socket before it is closed as a part of vm.wait(). Additionally, following two cosmetic changes have been made: - Removed VM QEMU command line logging as avocado framework already logs it. This is a minor cleanup along the way. - Update my email to my work email in the avocado acpi bios bits test. CC: jsnow@redhat.com Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231027032120.6012-3-anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry pointAni Sinha
QEMU defaults to 64-bit entry point since the following commit bf376f3020 ("hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models") The above change is applicable for all newer machine versions from version 8.1 and newer. i440fx and q35 machine versions 8.0 and older still use 32-bit entry points. Unfortunately, bits currently does not recognize 64-bit entry points and hence is not able to parse SMBIOS tables. Therefore, we need to enforce 32-bit SMBIOS entry point in QEMU command line so that bits is able to parse the SMBIOS tables. Once we implement the support in bits to parse 64-bit entry points, we can remove the extra command line that is passed to enforce a 32-bit entry point. The support can be added to the following smbios test script: tests/avocado/acpi-bits/bits-tests/smbios.py2 in QEMU repository. CC: jusual@redhat.com CC: imammedo@redhat.com Signed-off-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231027032120.6012-2-anisinha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread ↵Zhao Liu
count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000CA6 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[434h 1076 1] Subtable Type : 00 [Processor Local APIC] +[435h 1077 1] Length : 08 +[436h 1078 1] Processor ID : 81 +[437h 1079 1] Local Apic ID : 81 +[438h 1080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 [snip] +[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC] +[C4Dh 3149 1] Length : 10 +[C4Eh 3150 2] Reserved : 0000 +[C50h 3152 4] Processor x2Apic ID : 00000181 +[C54h 3156 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[C58h 3160 4] Processor UID : 00000103 + +[C5Ch 3164 1] Subtable Type : 01 [I/O APIC] +[C5Dh 3165 1] Length : 0C +[C5Eh 3166 1] I/O Apic ID : 00 +[C5Fh 3167 1] Reserved : 00 +[C60h 3168 4] Address : FEC00000 +[C64h 3172 4] Interrupt : 00000000 + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 [snip] +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000083EA (33770) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x01 + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C081, 0x81, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x81)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x81) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x81, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 thread count2Zhao Liu
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is more than 255, then smbios type4 table encodes threads per socket into the thread count2 field. So for the topology in this case, there're the following considerations: 1. threads per socket should be more than 255 to ensure we could cover the thread count2 field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count2 field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count2 field. Note we don't consider the topology with multiple sockets since this topology would create too many vCPUs (more than 255 threads per socket with at least 2 sockets, which may cause the failure "Number of hotpluggable cpus requested (*) exceeds the maximum cpus supported by KVM (*) socket_accept failed: Resource temporarily unavailable"), and the calculation of threads per socket has already been covered by "thread count" test case. Based on these considerations, select the topology as the follow: -smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2 The expected thread count2 = threads per socket = threads (2) * cores (65) * dies (2) = 260. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-16-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu
thread count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count2 field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread ↵Zhao Liu
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 63 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 thread countZhao Liu
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is not more than 255, then smbios type4 table encodes threads per socket into the thread count field. So for the topology in this case, there're the following considerations: 1. threads per socket should be not more than 255 to ensure we could cover the thread count field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count field. Based on these considerations, select the topology as the follow: -smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3 The expected thread count = threads per socket = threads (3) * cores (3) * dies (3) = 27. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-13-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu
thread count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the thread count field of smbios type4 table. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Update ACPI table binaries for smbios core count2 testZhao Liu
Change the core count2 from 275 to 260. Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: APIC: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023 * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 4] Table Length : 000009AE +[004h 0004 4] Table Length : 00000CA6 [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : CE +[009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : FEE00000 [028h 0040 4] Flags (decoded below) : 00000001 PC-AT Compatibility : 1 [02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] [02Dh 0045 1] Length : 08 [02Eh 0046 1] Processor ID : 00 [02Fh 0047 1] Local Apic ID : 00 [030h 0048 4] Flags (decoded below) : 00000001 Processor Enabled : 1 @@ -1051,1256 +1051,1136 @@ [42Ch 1068 1] Subtable Type : 00 [Processor Local APIC] [42Dh 1069 1] Length : 08 [42Eh 1070 1] Processor ID : 80 [42Fh 1071 1] Local Apic ID : 80 [430h 1072 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 [434h 1076 1] Subtable Type : 00 [Processor Local APIC] [435h 1077 1] Length : 08 [436h 1078 1] Processor ID : 81 [437h 1079 1] Local Apic ID : 81 [438h 1080 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 -[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC] -[43Dh 1085 1] Length : 08 -[43Eh 1086 1] Processor ID : 82 -[43Fh 1087 1] Local Apic ID : 82 -[440h 1088 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 - -[444h 1092 1] Subtable Type : 00 [Processor Local APIC] -[445h 1093 1] Length : 08 -[446h 1094 1] Processor ID : 83 -[447h 1095 1] Local Apic ID : 83 -[448h 1096 4] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Runtime Online Capable : 0 [snip] - -[964h 2404 1] Subtable Type : 01 [I/O APIC] -[965h 2405 1] Length : 0C -[966h 2406 1] I/O Apic ID : 00 -[967h 2407 1] Reserved : 00 -[968h 2408 4] Address : FEC00000 -[96Ch 2412 4] Interrupt : 00000000 - -[970h 2416 1] Subtable Type : 02 [Interrupt Source Override] -[971h 2417 1] Length : 0A -[972h 2418 1] Bus : 00 -[973h 2419 1] Source : 00 -[974h 2420 4] Interrupt : 00000002 -[978h 2424 2] Flags (decoded below) : 0000 +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082 + +[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC] +[44Dh 1101 1] Length : 10 +[44Eh 1102 2] Reserved : 0000 +[450h 1104 4] Processor x2Apic ID : 00000101 +[454h 1108 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[458h 1112 4] Processor UID : 00000083 + [snip] + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override] -[97Bh 2427 1] Length : 0A -[97Ch 2428 1] Bus : 00 -[97Dh 2429 1] Source : 05 -[97Eh 2430 4] Interrupt : 00000005 -[982h 2434 2] Flags (decoded below) : 000D +[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override] +[C73h 3187 1] Length : 0A +[C74h 3188 1] Bus : 00 +[C75h 3189 1] Source : 05 +[C76h 3190 4] Interrupt : 00000005 +[C7Ah 3194 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[984h 2436 1] Subtable Type : 02 [Interrupt Source Override] -[985h 2437 1] Length : 0A -[986h 2438 1] Bus : 00 -[987h 2439 1] Source : 09 -[988h 2440 4] Interrupt : 00000009 -[98Ch 2444 2] Flags (decoded below) : 000D +[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override] +[C7Dh 3197 1] Length : 0A +[C7Eh 3198 1] Bus : 00 +[C7Fh 3199 1] Source : 09 +[C80h 3200 4] Interrupt : 00000009 +[C84h 3204 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override] -[98Fh 2447 1] Length : 0A -[990h 2448 1] Bus : 00 -[991h 2449 1] Source : 0A -[992h 2450 4] Interrupt : 0000000A -[996h 2454 2] Flags (decoded below) : 000D +[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override] +[C87h 3207 1] Length : 0A +[C88h 3208 1] Bus : 00 +[C89h 3209 1] Source : 0A +[C8Ah 3210 4] Interrupt : 0000000A +[C8Eh 3214 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[998h 2456 1] Subtable Type : 02 [Interrupt Source Override] -[999h 2457 1] Length : 0A -[99Ah 2458 1] Bus : 00 -[99Bh 2459 1] Source : 0B -[99Ch 2460 4] Interrupt : 0000000B -[9A0h 2464 2] Flags (decoded below) : 000D +[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI] -[9A3h 2467 1] Length : 0C -[9A4h 2468 2] Flags (decoded below) : 0000 +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[9A6h 2470 4] Processor UID : FFFFFFFF -[9AAh 2474 1] Interrupt Input LINT : 01 -[9ABh 2475 3] Reserved : 000000 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000 ... DSDT: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51 2023 + * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023 * * Original Table Header: * Signature "DSDT" - * Length 0x00007EEF (32495) + * Length 0x000083EA (33770) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x52 + * Checksum 0x01 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -4196,107 +4196,32 @@ } If ((Arg0 == 0x0101)) { Notify (C101, Arg1) } If ((Arg0 == 0x0102)) { Notify (C102, Arg1) } If ((Arg0 == 0x0103)) { Notify (C103, Arg1) } - - If ((Arg0 == 0x0104)) - { - Notify (C104, Arg1) - } - - If ((Arg0 == 0x0105)) - { - Notify (C105, Arg1) - } - - If ((Arg0 == 0x0106)) - { - Notify (C106, Arg1) - } - [snip] - If ((Arg0 == 0x0112)) - { - Notify (C112, Arg1) - } } Method (CSTA, 1, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) \_SB.PCI0.PRES.CSEL = Arg0 Local0 = Zero If ((\_SB.PCI0.PRES.CPEN == One)) { Local0 = 0x0F } Release (\_SB.PCI0.PRES.CPLK) Return (Local0) } @@ -4306,33 +4231,33 @@ \_SB.PCI0.PRES.CSEL = Arg0 \_SB.PCI0.PRES.CEJ0 = One Release (\_SB.PCI0.PRES.CPLK) } Method (CSCN, 0, Serialized) { Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) Name (CNEW, Package (0xFF) {}) Local3 = Zero Local4 = One While ((Local4 == One)) { Local4 = Zero Local0 = One Local1 = Zero - While (((Local0 == One) && (Local3 < 0x0113))) + While (((Local0 == One) && (Local3 < 0x0104))) { Local0 = Zero \_SB.PCI0.PRES.CSEL = Local3 \_SB.PCI0.PRES.CCMD = Zero If ((\_SB.PCI0.PRES.CDAT < Local3)) { Break } If ((Local1 == 0xFF)) { Local4 = One Break } Local3 = \_SB.PCI0.PRES.CDAT @@ -7220,3281 +7145,3281 @@ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry { 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x81) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x81, Arg0, Arg1, Arg2) } } - Processor (C082, 0x82, 0x00000000, 0x00) + Device (C082) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x82) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x82)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x82) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x82, Arg0, Arg1, Arg2) } } - Processor (C083, 0x83, 0x00000000, 0x00) + Device (C083) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x83) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x83)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x83) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x83, Arg0, Arg1, Arg2) } } - Processor (C084, 0x84, 0x00000000, 0x00) + Device (C084) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x84) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0x84)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0x84) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0x84, Arg0, Arg1, Arg2) } } [snip] - Processor (C0FE, 0xFE, 0x00000000, 0x00) + Device (C0FE) { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0xFE) // _UID: Unique ID Method (_STA, 0, Serialized) // _STA: Status { Return (CSTA (0xFE)) } - Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry { - 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........ + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00, 0x00, // ....|... + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00 // ........ }) Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 { CEJ0 (0xFE) } Method (_OST, 3, Serialized) // _OST: OSPM Status Indication { COST (0xFE, Arg0, Arg1, Arg2) } } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Extend smbios core count2 test to cover general ↵Zhao Liu
topology The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed the miscalculation of cores per socket. The original core count2 test (with the topology configured by "-smp 275") didn't recognize that topology-related but because it just created a special topology with only one socket and one die by default, ignoring the effect of more topology levels (between socket and core) on the cores per socket calculation. So for the topology in this case, there're the following considerations: 1. cores per socket should be more than 255 to ensure we could cover the core count2 field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (multiple sockets or dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count2 field is correct. Based on these considerations, select the topology with multiple dies: -smp 260,dies=2,cores=130,threads=1 Note, here we doesn't configure multiple sockets to avoid the error ("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user uses the default ulimit seeting on his machine. And the cores per socket calculation for multiple sockets has already been covered by the core count test case, so that only multiple dies configuration is enough. The expected core count2 = cores per socket = cores (130) * dies (2) = 260. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-10-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core ↵Zhao Liu
count2 test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be changed about the type 4 core count2 test case. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count ↵Zhao Liu
test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 3C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01 ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } [snip] + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } [snip] + If ((Arg0 == 0x35)) + { + Notify (C035, Arg1) + } + } [snip] + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + } ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 core countZhao Liu
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in type4"). In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of cores in the socket is not more than 255, then smbios type4 table encodes cores per socket into the core count field. So for the topology in this case, there're the following considerations: 1. cores per socket should be not more than 255 to ensure we could cover the core count field. 2. The original bug was that cores per socket was miscalculated, so now we should include as many topology levels as possible (mutiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the cores per socket encoded in the core count field is correct. Based on these considerations, select the topology with multiple sockets and dies: -smp 54,sockets=2,dies=3,cores=3,threads=3 The expected core count = cores per socket = cores (3) * dies (3) = 9. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-7-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core ↵Zhao Liu
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 core count field. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add ACPI table binaries for smbios type4 count testZhao Liu
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. Changes in the tables: FACP: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + ... APIC: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000430 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : C5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 [snip] +[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC] +[3E5h 0997 1] Length : 08 +[3E6h 0998 1] Processor ID : 77 +[3E7h 0999 1] Local Apic ID : 9E +[3E8h 1000 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[3ECh 1004 1] Subtable Type : 01 [I/O APIC] +[3EDh 1005 1] Length : 0C +[3EEh 1006 1] I/O Apic ID : 00 +[3EFh 1007 1] Reserved : 00 +[3F0h 1008 4] Address : FEC00000 +[3F4h 1012 4] Interrupt : 00000000 + +[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override] +[3F9h 1017 1] Length : 0A +[3FAh 1018 1] Bus : 00 +[3FBh 1019 1] Source : 00 +[3FCh 1020 4] Interrupt : 00000002 +[400h 1024 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[402h 1026 1] Subtable Type : 02 [Interrupt Source Override] +[403h 1027 1] Length : 0A +[404h 1028 1] Bus : 00 +[405h 1029 1] Source : 05 +[406h 1030 4] Interrupt : 00000005 +[40Ah 1034 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override] +[40Dh 1037 1] Length : 0A +[40Eh 1038 1] Bus : 00 +[40Fh 1039 1] Source : 09 +[410h 1040 4] Interrupt : 00000009 +[414h 1044 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[416h 1046 1] Subtable Type : 02 [Interrupt Source Override] +[417h 1047 1] Length : 0A +[418h 1048 1] Bus : 00 +[419h 1049 1] Source : 0A +[41Ah 1050 4] Interrupt : 0000000A +[41Eh 1054 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[420h 1056 1] Subtable Type : 02 [Interrupt Source Override] +[421h 1057 1] Length : 0A +[422h 1058 1] Bus : 00 +[423h 1059 1] Source : 0B +[424h 1060 4] Interrupt : 0000000B +[428h 1064 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI] +[42Bh 1067 1] Length : 06 +[42Ch 1068 1] Processor ID : FF +[42Dh 1069 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[42Fh 1071 1] Interrupt Input LINT : 01 + ... DSDT: +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000489D (18589) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xDB + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + [snip] + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } [snip] + Processor (C077, 0x77, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x77)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 // ..w..... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x77) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x77, Arg0, Arg1, Arg2) + } + } + } + } + ... Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Add test for smbios type4 countZhao Liu
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets calculation"). In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built for each socket, so the count of type4 tables should be equal to the number of sockets. Thus for the topology in this case, there're the following considerations: 1. The topology should include multiple sockets to ensure smbios could create type4 tables for each socket. 2. In addition to sockets, for the more general topology, we should also configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it), to ensure that smbios is able to exclude the effect of other topology levels to create the type4 tables only for sockets. 3. The original miscalculation bug also misused "smp.cpus", so it's necessary to configure "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) as well to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of the count of type4 tables. Based on these considerations, select the topology as the follow: -smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3 The expected count of type4 tables = sockets (5). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-4-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: bios-tables-test: Prepare the ACPI table change for smbios type4 ↵Zhao Liu
count test Following the guidelines in tests/qtest/bios-tables-test.c, this is step 1 - 3. List the ACPI tables that will be added to test the type 4 count. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07tests: test-smp-parse: Add the test for cores/threads per socket helpersZhao Liu
Use the different ways to calculate cores/threads per socket, so that the new CPU topology levels won't be missed in these 2 helpes: * machine_topo_get_cores_per_socket() * machine_topo_get_threads_per_socket() Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/ threads per socket"). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-2-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 12:57:41 +0000