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2023-05-18Hexagon (tests/tcg/hexagon) Add v73 scalar testsTaylor Simpson
Tests added for the following instructions J2_callrh J2_jumprh Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-10-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v69 HVX testsTaylor Simpson
The following instructions are tested V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-8-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v68 HVX testsTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-6-tsimpson@quicinc.com>
2023-05-18Hexagon (tests/tcg/hexagon) Add v68 scalar testsTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-4-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
2023-05-18tests/tcg/i386: correct mask for VPERM2F128/VPERM2I128Paolo Bonzini
The instructions also use bits 3 and 7 of their 8-byte immediate. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-16tests/tcg/s390x: Test EXECUTE of relative branchesIlya Leoshkevich
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230426235813.198183-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-16tests/tcg/s390x: Enable the multiarch system testsIlya Leoshkevich
Multiarch tests are written in C and need support for printing characters. Instead of implementing the runtime from scratch, just reuse the pc-bios/s390-ccw one. Run tests with -nographic in order to enable SCLP (enable this for the existing tests as well, since it does not hurt). Use the default linker script for the new tests. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230511114651.439872-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-16tests/tcg/multiarch: Make the system memory test work on big-endianIlya Leoshkevich
Store the bytes in descending order on big-endian. Invert the logic in the multi-byte signed tests on big-endian. Make the checks in the multi-byte signed tests stricter. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230511114651.439872-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-05tests: tcg: ppc64: Add tests for Vector Extract Mask InstructionsShivaprasad G Bhat
Add test for vextractbm, vextractwm, vextractdm and vextractqm instructions. Test works for both qemu-ppc64 and qemu-ppc64le. Based on the test case written by John Platts posted at [1] References: [1] - https://gitlab.com/qemu-project/qemu/-/issues/1536 Signed-off-by: John Platts <john_platts@hotmail.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <168319294881.1159309.17060400720026083557.stgit@ltc-boston1.aus.stglabs.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-04-27tests/tcg: limit the scope of the plugin testsAlex Bennée
Running every plugin with every test is getting excessive as well as not really improving coverage that much. Restrict the plugin tests to just the MULTIARCH_TESTS which are shared between most architecture for both system and user-mode. For those that aren't we need to squash MULTIARCH_TESTS so we don't add them when they are not part of the TESTS global. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230424092249.58552-14-alex.bennee@linaro.org>
2023-04-21Hexagon (tests/tcg/hexagon) Move HVX test infra to header fileTaylor Simpson
This will facilitate adding additional tests in separate .c files Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230406174241.853296-1-tsimpson@quicinc.com>
2023-04-21Hexagon (target/hexagon) Add overrides for count trailing zeros/onesTaylor Simpson
The following instructions are overriden S2_ct0 Count trailing zeros S2_ct1 Count trailing ones S2_ct0p Count trailing zeros (register pair) S2_ct1p Count trailing ones (register pair) These instructions are not handled by idef-parser because the imported semantics uses bit-reverse. However, they are straightforward to implement in TCG with tcg_gen_ctzi_* Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405164211.30015-1-tsimpson@quicinc.com>
2023-03-22tests/tcg: add some help output for running individual testsAlex Bennée
So you can do: cd tests/tcg/aarch64-linux-user make -f ../Makefile.target help To see the list of tests. You can then run each one individually. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230315174331.2959-8-alex.bennee@linaro.org>
2023-03-20tests/tcg/s390x: Test unaligned accessesIlya Leoshkevich
Add a number of small test that check whether accessing unaligned addresses in various ways leads to a specification exception. Run these test both in softmmu and user configurations; expect a PGM in one case and SIGILL in the other. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230316164428.275147-13-iii@linux.ibm.com> [thuth: Added -Wl,--build-id=none to LDFLAGS] Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add ex-relative-long.cIlya Leoshkevich
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions as targets. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Message-Id: <20230316210751.302423-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add rxsbg.cIlya Leoshkevich
Add a small test for RXSBG with T=1 to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230316172205.281369-3-iii@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-20tests/tcg/s390x: Add PSW modification testsIlya Leoshkevich
Add several small tests that check the PSW modification instructions: * lpsw.S checks whether LPSW works correctly in the "happy" case. * lpswe-early.S checks whether early exceptions are recognized and whether the correct ILC and old PSW are stored when they happen. * ssm-early.S, stosm-early.S and exrl-ssm-early.S check the special handling of SSM and STOSM with respect to early exceptions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230315020408.384766-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-15tests/tcg/xtensa: allow testing big-endian coresMax Filippov
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2023-03-15tests/tcg/xtensa: add linker.ld to CLEANFILESMax Filippov
Linker script for xtensa tests must be preprocessed for a specific target, remove it as a part of make clean. Fixes: be5cac175a ("tests/tcg/xtensa: enable system tests") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-13tests/tcg/s390x: Add C(G)HRL testNina Schoetterl-Glausch
Test COMPARE HALFWORD RELATIVE LONG instructions. Test that the bytes following the second operand do not affect the instruction. Test the sign extension performed on the second operand. Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230310114157.3024170-3-nsg@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-10Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into stagingPeter Maydell
Hexagon (target/hexagon) update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmQGzGYACgkQewJE+xLe # RCJfxggAgAY9fqUxKk5FxziMX6sVxx2SiYGU1biABtHyduQvJ43U7In4cnbC65FL # Pn+ZSixPRh51Ij2s9FTzDQ8IUNt/k1W7gCoEC3I0wDbQHdICEIlx30ry68QlUgOa # T6ZDquJkanwFjb7kMnyM4LRBBxLG+OuYvKe1e+nzun0LDlfTS/sHitRlf4AJEBOK # 9h/Bdy81RcWlLzlc5tmD0f9rhtmkkFCTu/TGLt4G6sfn1xZbRdh5N1cFfUShPlQM # qAgj+JgBOQoPKaBhQZnA3Ps9ZEM4+/8KPsr5oGweAcjqD8+kMGCmi2jv+60ES5Uq # EDpn25COw7BVAo6vP/JfBEiZTg+YpA== # =FDSG # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Mar 2023 05:32:22 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230306' of https://github.com/quic/qemu: Hexagon (target/hexagon) Improve code gen for predicated HVX instructions Hexagon (target/hexagon) Reduce manipulation of slot_cancelled Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair] Hexagon (target/hexagon) Change subtract from zero to change sign Hexagon (tests/tcg/hexagon) Enable HVX tests Hexagon (tests/tcg/hexagon) Remove __builtin from scatter_gather Hexagon (tests/tcg/hexagon) Update preg_alias.c Hexagon (target/hexagon) Analyze packet for HVX Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed Hexagon (target/hexagon) Analyze packet before generating TCG Hexagon (target/hexagon) Add overrides for dealloc-return instructions Hexagon (target/hexagon) Add overrides for endloop1/endloop01 Hexagon (target/hexagon) Add overrides for callr Hexagon (target/hexagon) Add overrides for jumpr31 instructions target/hexagon/idef-parser: Remove unused code paths target/hexagon/idef-parser: Elide mov in gen_pred_assign Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-07testing: probe gdb for supported architectures ahead of timeAlex Bennée
Currently when we encounter a gdb that is old or not built with multiarch in mind we fail rather messily. Try and improve the situation by probing ahead of time and setting HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip and give a more meaningful message if we don't run the test. Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230302190846.2593720-24-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-24-richard.henderson@linaro.org>
2023-03-06Hexagon (target/hexagon) Change subtract from zero to change signTaylor Simpson
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly handle -0. Previously we would negate the input operand by subtracting from zero. Instead, we negate by changing the sign bit. Test case added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-12-tsimpson@quicinc.com>
2023-03-06Hexagon (tests/tcg/hexagon) Enable HVX testsTaylor Simpson
Made possible by new toolchain container Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-11-tsimpson@quicinc.com>
2023-03-06Hexagon (tests/tcg/hexagon) Remove __builtin from scatter_gatherTaylor Simpson
Replace __builtin_* with inline assembly The __builtin's are subject to change with different compiler releases, so might break Mark arrays as aligned when accessed as HVX vectors Clean up comments Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-10-tsimpson@quicinc.com>
2023-03-06Hexagon (tests/tcg/hexagon) Update preg_alias.cTaylor Simpson
Add control registers (c4, c5) to clobbers list Made possible by new toolchain container Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-9-tsimpson@quicinc.com>
2023-03-01tests/docker: Use binaries for debian-tricore-crossBastian Koppelmann
since binutils is pretty old, it fails our CI repeatedly during the compilation of tricore-binutils. We created a precompiled version using the debian docker image and download it instead of building it ourself. We also updated the package to include a newer version of binutils, gcc, and newlib. The default TriCore ISA version used by tricore-as changed from the old version, so we have to specify it now. If we don't 'test_fadd' fails with 'unknown opcode'. The new assembler also picks a new encoding in ld.h which fails the 'test_ld_h' test. We fix that by using the newest TriCore CPU for QEMU. The old assembler accepted an extra ')' in 'test_imask'. The new one does not, so lets remove it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230209145812.46730-1-kbastian@mail.uni-paderborn.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230228190653.1602033-12-alex.bennee@linaro.org>
2023-02-27Merge tag 'for-upstream-8.0' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* New Sapphire Rapids model support * x86 bugfixes * Prepare to drop support for Python 3.6 # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmP87gcUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroM+TAf/TcRrukw+FXUs0Ld3AadRY6g3xV2x # n1VIfkMC2Bp1LVOS1W9aw7V6jPg8KMAV9SCQJjsVtyB5E9yPQg+/w7UgexqISYQG # 7NK3jDXmslSGIHNHh4qH9xAjQGjw/6e7N/gyWP+99vHPwZSbFJT6k7KP0/3O9yCu # /9KINq8AvvGbfW5m2d/umV1v1Gq4KwXkTa5uVIOciDMJtaA0QjADHg1MqsHPzBUP # F4du5BbuMaJkgQgJV5zsn7W9NnEQt1XzSug1c/vp2vyqEV00L4TjL9BzTqsTEBtS # KjUcQif5R5a+o8QRND9j8f74xjFpOR/nAEleNsfo6iwZQwWAiBQZ8ETsew== # =2aMG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Feb 2023 17:53:11 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream-8.0' of https://gitlab.com/bonzini/qemu: i386: Add new CPU model SapphireRapids target/i386: KVM: allow fast string operations if host supports them target/i386: add FZRM, FSRS, FSRC target/i386: add FSRM to TCG MAINTAINERS: Cover RCU documentation ci, docker: update CentOS and OpenSUSE Python to non-EOL versions docs/devel: update and clarify lcitool instructions lcitool: update submodule configure: Look for auxiliary Python installations configure: protect against escaping venv when running Meson meson: stop looking for 'sphinx-build-3' meson: Avoid duplicates in generated config-poison.h again target/i386: Fix BZHI instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27target/i386: Fix BZHI instructionRichard Henderson
We did not correctly handle N >= operand size. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114233206.3118472-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-27tests/tcg/s390x: Add sam.SIlya Leoshkevich
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221129015328.55439-1-iii@linux.ibm.com> Message-Id: <20230220184052.163465-7-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-27tests/tcg/s390x: Add bal.SIlya Leoshkevich
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221103130011.2670186-1-iii@linux.ibm.com> Message-Id: <20230220184052.163465-6-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-16target/i386: Fix 32-bit AD[CO]X insns in 64-bit modeRichard Henderson
Failure to truncate the inputs results in garbage for the carry-out. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1373 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230115012103.3131796-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* block/iscsi: fix double-free on BUSY or similar statuses * catch [accel] entry without accelerator * target/i386: various fixes for BMI and ADX instructions * make the contents of meson-buildoptions.sh stable # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmPpDTcUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroODWAgAhWi0XSBe91+34ahQqx6JoLStNX9e # xy1Cm/5LPDrDquD/4T6gnzb1Min/X2AsVu9c+VIbuHbL/rFc7aNIEL6c7KzwSFLs # vEDF7tSnlIMK0ClDsDYBz7HUIgBgqE2crAJmTJus2Cqd+Ef5bMxhQi5Imrk6qtmO # HRdVYEGasJ7CO50oUB91AMrNInWQw0qBnBOB8TnwTLTcvE1txa+xnZuZgQA2HrGX # OweLdKRcYPvRYvBB3wLMbwqEKbD1eYbdbNt7T2KkuVQpYcgfoCpayHIIMroD+hvu # BImmG9wWieDKH4Brs765gH6/3VF5UZKbgDQo9Wz+W/5QqnqRSsOYBiMkmA== # =G3PN # -----END PGP SIGNATURE----- # gpg: Signature made Sun 12 Feb 2023 16:00:55 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: libqtest: ensure waitpid() is only called once libqtest: split qtest_spawn_qemu function target/i386: fix ADOX followed by ADCX target/i386: Fix C flag for BLSI, BLSMSK, BLSR target/i386: Fix BEXTR instruction tests/tcg/i386: Introduce and use reg_t consistently vl: catch [accel] entry without accelerator block/iscsi: fix double-free on BUSY or similar statuses remove unnecessary extern "C" blocks build: make meson-buildoptions.sh stable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-14tests/tcg/s390x: Use -nostdlib for softmmu testsIlya Leoshkevich
The code currently uses -nostartfiles, but this does not prevent linking with libc. On Fedora there is no cross-libc, so the linking step fails. Fix by using the more comprehensive -nostdlib (that's also what probe_target_compiler() checks for as well). Fixes: 503e549e441e ("tests/tcg/s390x: Test unaligned accesses to lowcore") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230131182057.2261614-1-iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-02-11target/i386: fix ADOX followed by ADCXPaolo Bonzini
When ADCX is followed by ADOX or vice versa, the second instruction's carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX operation. Retrieving the carry from EFLAGS is handled by this bit of gen_ADCOX: tcg_gen_extract_tl(carry_in, cpu_cc_src, ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); Unfortunately, in this case cc_op has been overwritten by the previous "if" statement to CC_OP_ADCOX. This works by chance when the first instruction is ADCX; however, if the first instruction is ADOX, ADCX will incorrectly take its carry from OF instead of CF. Fix by moving the computation of the new cc_op at the end of the function. The included exhaustive test case fails without this patch and passes afterwards. Because ADCX/ADOX need not be invoked through the VEX prefix, this regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement 0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a little earlier, when BMI instructions were rewritten using the new decoder framework. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471 Reported-by: Paul Jolly <https://gitlab.com/myitcv> Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11target/i386: Fix BEXTR instructionRichard Henderson
There were two problems here: not limiting the input to operand bits, and not correctly handling large extraction length. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1372 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114230542.3116013-3-richard.henderson@linaro.org> Cc: qemu-stable@nongnu.org Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-11tests/tcg/i386: Introduce and use reg_t consistentlyRichard Henderson
Define reg_t based on the actual register width. Define the inlines using that type. This will allow input registers to 32-bit insns to be set to 64-bit values on x86-64, which allows testing various edge cases. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230114230542.3116013-2-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-02-08tests/tcg/tricore: Add test for ld.hBastian Koppelmann
this exercises the error reported in https://gitlab.com/qemu-project/qemu/-/issues/652. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230203132132.511254-1-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add LD.BU testsBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-11-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR testsBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-9-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add tests for RRPW_DEXTRBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-7-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERTBastian Koppelmann
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So let's make each register unique. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-08tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASKBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230202120432.1268-3-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2023-02-04target/s390x: Use a single return for helper_divs64/u64Richard Henderson
Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Extended div test case to cover these insns.
2023-02-04tests/tcg/s390x: Add cdsg.cIlya Leoshkevich
Add a simple test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230201133257.3223115-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add long-double.cRichard Henderson
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add clst.cIlya Leoshkevich
Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-04tests/tcg/s390x: Add div.cIlya Leoshkevich
Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-02tests/tcg: add memory-sve test for aarch64Alex Bennée
This will be helpful in debugging problems with tracking SVE memory accesses via the TCG plugins system. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Robert Henry <robhenry@microsoft.com> Cc: Aaron Lindsay <aaron@os.amperecomputing.com> Message-Id: <20230124180127.1881110-26-alex.bennee@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 11:38:11 +0000