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2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-29tests/tcg: really fix path to target configurationPaolo Bonzini
This was attempted in commit 533b0a1a41 ("tests/tcg: Fix target-specific Makefile variables path for user-mode", 2022-01-12) but it also used the wrong path; default.mak is used for config/devices, not config/targets. While at it, explain what the inclusion is about. Cc: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-18target/arm: Fix sve2 ldnt1 and stnt1Richard Henderson
For both ldnt1 and stnt1, the meaning of the Rn and Rm are different from ld1 and st1: the vector and integer registers are reversed, and the integer register 31 refers to XZR instead of SP. Secondly, the 64-bit version of ldnt1 was being interpreted as 32-bit unpacked unscaled offset instead of 64-bit unscaled offset, which discarded the upper 32 bits of the address coming from the vector argument. Thirdly, validate that the memory element size is in range for the vector element size for ldnt1. For ld1, we do this via independent decode patterns, but for ldnt1 we need to do it manually. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220308031655.240710-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-16tests/tcg/s390x: Test BRASL and BRCL with large negative offsetsIlya Leoshkevich
Add a small test in order to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20220314104232.675863-4-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-16tests/tcg: drop -cpu max from s390x sha512-mvx invocationAlex Bennée
With -cpu max we get a warning: qemu-s390x: warning: 'msa5-base' requires 'kimd-sha-512'. But dropping the -cpu max and it still runs fine. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220309112248.4083619-1-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-15Merge tag 'pull-ppc-20220314' of https://github.com/legoater/qemu into stagingPeter Maydell
ppc-7.0 queue : * Removal of user-created PHB devices * Avocado fixes for --disable-tcg * Instruction and Radix MMU fixes # gpg: Signature made Mon 14 Mar 2022 15:16:07 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20220314' of https://github.com/legoater/qemu: ppc/pnv: Remove user-created PHB{3,4,5} devices ppc/pnv: Always create the PHB5 PEC devices ppc/pnv: Introduce a pnv-phb5 device to match root port ppc/xive2: Make type Xive2EndSource not user creatable target/ppc: fix xxspltw for big endian hosts target/ppc: fix ISI fault cause for Radix MMU avocado/ppc_virtex_ml507.py: check TCG accel in test_ppc_virtex_ml507() avocado/ppc_prep_40p.py: check TCG accel in all tests avocado/ppc_mpc8544ds.py: check TCG accel in test_ppc_mpc8544ds() avocado/ppc_bamboo.py: check TCG accel in test_ppc_bamboo() avocado/ppc_74xx.py: check TCG accel for all tests avocado/ppc_405.py: check TCG accel in test_ppc_ref405ep() avocado/ppc_405.py: remove test_ppc_taihu() avocado/boot_linux_console.py: check TCG accel in test_ppc_mac99() avocado/boot_linux_console.py: check TCG accel in test_ppc_g3beige() avocado/replay_kernel.py: make tcg-icount check in run_vm() avocado/boot_linux_console.py: check tcg accel in test_ppc64_e500 avocado/boot_linux_console.py: check for tcg in test_ppc_powernv8/9 qtest/meson.build: check CONFIG_TCG for boot-serial-test in qtests_ppc qtest/meson.build: check CONFIG_TCG for prom-env-test in qtests_ppc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-14target/ppc: fix xxspltw for big endian hostsMatheus Ferst
Fix a typo in the host endianness macro and add a simple test to detect regressions. Fixes: 9bb0048ec6f8 ("target/ppc: convert xxspltw to vector operations") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220310172047.61094-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-12Hexagon (target/hexagon) assignment to c4 should wait until packet commitTaylor Simpson
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to c4 inside a packet with reads from predicate registers, the predicate reads should get the old values. Test case added to tests/tcg/hexagon/preg_alias.c Co-authored-by: Michael Lambert <mlambert@cuicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-13-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) fix bug in conv_df2uw_chopTaylor Simpson
Fix typo that checked for 32 bit nan instead of 64 bit Test case added in tests/tcg/hexagon/usr.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-11-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) fix inline asm in preg_alias.cTaylor Simpson
Replace consecutive inline asm blocks with a single one with proper outputs/inputs/clobbers rather than making assumptions about register values being carried between separate blocks. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-10-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) update overflow testTaylor Simpson
Add a test that sets USR multiple times in a packet Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-9-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) add floating point instructions to usr.cTaylor Simpson
Tests to confirm floating point instructions are properly setting exception bits in USR Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-8-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) test instructions that might set bits in USRTaylor Simpson
Hexagon has ~200 instructions that set the saturate bit in USR, these were broken into groups of similar instructions and one instruction from each group is tested with at least one input that does not saturate and at least one input that does saturate. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-7-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) properly handle NaN in dfmin/dfmax/sfmin/sfmaxTaylor Simpson
The float??_minnum implementation differs from Hexagon for SNaN, it returns NaN, but Hexagon returns the other input. So, we use float??_minimum_number. Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220308190410.22355-1-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) properly handle denorm in arch_sf_recip_commonTaylor Simpson
The arch_sf_recip_common function was calling float32_getexp which adjusts for denorm, but the we actually need the raw exponent bits. This function is called from 3 instructions sfrecipa sffixupn sffixupd Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-6-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon HVX (target/hexagon) fix bug in HVX saturate instructionsTaylor Simpson
Two tests added to tests/tcg/hexagon/hvx_misc.c v21.uw = vadd(v11.uw, v10.uw):sat v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-3-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) fix bug in circular addressingMichael Lambert
Versions V3 and earlier should treat the "K_const" and "length" values as unsigned. Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug Signed-off-by: Michael Lambert <mlambert@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-2-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-09Merge remote-tracking branch ↵Peter Maydell
'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging linux-user pull request 20220308 deliver SIGTRAP on POWERPC_EXCP_TRAP remove stale "not threadsafe" comments # gpg: Signature made Tue 08 Mar 2022 15:02:14 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request: tests/tcg/ppc64le: change signal_save_restore_xer to use SIGTRAP linux-user/ppc: deliver SIGTRAP on POWERPC_EXCP_TRAP linux-user: Remove stale "not threadsafe" comments Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-08tests/tcg/ppc64le: change signal_save_restore_xer to use SIGTRAPMatheus Ferst
Now that linux-user delivers the signal on tw, we can change signal_save_restore_xer to use SIGTRAP instead of SIGILL. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220113170456.1796911-3-matheus.ferst@eldorado.org.br> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-03-07tests/tcg/s390x: Cleanup of mie3 tests.David Miller
Adds clobbers and merges remaining separate asm statements. Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220301214305.2778-1-dmiller423@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [thuth: dropped changes to mie3-compl.c, whitespace fixes] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-07tests/tcg/s390x: Fix the exrl-trt* tests with ClangThomas Huth
The exrl-trt* tests use two pre-initialized variables for the results of the assembly code: uint64_t r1 = 0xffffffffffffffffull; uint64_t r2 = 0xffffffffffffffffull; But then the assembly code copies over the full contents of the register into the output variable, without taking care of this pre-initialized values: " lgr %[r1],%%r1\n" " lgr %[r2],%%r2\n" The code then finally compares the register contents to a value that apparently depends on the pre-initialized values: if (r2 != 0xffffffffffffffaaull) { write(1, "bad r2\n", 7); return 1; } This all works with GCC, since the 0xffffffffffffffff got into the r2 register there by accident, but it fails completely with Clang. Let's fix this by declaring the r1 and r2 variables as proper register variables instead, so the pre-initialized values get correctly passed into the inline assembly code. Message-Id: <20220301092431.1448419-1-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-07tests/tcg/s390x: Fix mvc, mvo and pack tests with ClangThomas Huth
These instructions use addressing with a "base address", meaning that if register r0 is used, it is always treated as zero, no matter what value is stored in the register. So we have to make sure not to use register r0 for these instructions in our tests. There was no problem with GCC so far since it seems to always pick other registers by default, but Clang likes to chose register r0, too, so we have to use the "a" constraint to make sure that it does not pick r0 here. Message-Id: <20220301093911.1450719-1-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-03-05tests/tcg/ppc64le: Use Altivec register names in clobber listMatheus Ferst
LLVM/Clang doesn't know the VSX registers when compiling with -mabi=elfv1. Use only registers >= 32 and list them with their Altivec name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: emit bcdsub with .long when neededMatheus Ferst
Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the absence of other means to detect this support at config-time, we resort to __has_builtin to identify the presence of __builtin_bcdsub at compile-time. If the builtin is not available, the instruction is emitted with a ".long". [1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html [2] https://github.com/llvm/llvm-project/commit/59eb767e11d4ffefb5f55409524e5c8416b2b0db [3] https://github.com/llvm/llvm-project/commit/c933c2eb334660c131f4afc9d194fafb0cec0423 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: drop __int128 usage in bcdsubMatheus Ferst
Using __int128 with inline asm constraints like "v" generates incorrect code when compiling with LLVM/Clang (e.g., only one doubleword of the VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and load the VSR with mtvsrd/xxmrghd. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsfMatheus Ferst
LLVM/Clang does not support __builtin_mtfsf. Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05Use long endian options for ppc64Miroslav Rezanina
GCC options pairs -mlittle/-mlittle-endian and -mbig/-mbig-endian are equivalent on ppc64 architecture. However, Clang supports only long version of the options. Use longer form in configure to properly support both GCC and Clang compiler. In addition, fix this issue in tcg test configure. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220131091714.4825-1-mrezanin@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-semihosting-280222-1' into staging Testing and semihosting updates: - restore TESTS/IMAGES filtering to docker tests - add NOUSER to alpine image - bump lcitool version - move arm64/s390x cross build images to lcitool - add aarch32 runner CI scripts - expand testing to more vectors - update s390x jobs to focal for gitlab/travis - disable threadcount for all sh4 - fix semihosting SYS_HEAPINFO and test # gpg: Signature made Mon 28 Feb 2022 18:46:41 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-semihosting-280222-1: tests/tcg: port SYS_HEAPINFO to a system test semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO tests/tcg: completely disable threadcount for sh4 gitlab: upgrade the job definition for s390x to 20.04 travis.yml: Update the s390x jobs to Ubuntu Focal tests/tcg: add vectorised sha512 versions tests/tcg: add sha512 test tests/tcg: build sha1-vector with O3 and compare tests/tcg/ppc64: clean-up handling of byte-reverse gitlab: add a new aarch32 custom runner definition scripts/ci: allow for a secondary runner scripts/ci: add build env rules for aarch32 on aarch64 tests/docker: introduce debian-riscv64-test-cross tests/docker: update debian-s390x-cross with lcitool tests/docker: update debian-arm64-cross with lcitool tests/lcitool: update to latest version tests/docker: add NOUSER for alpine image tests/docker: restore TESTS/IMAGES filtering Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tests/tcg: port SYS_HEAPINFO to a system testAlex Bennée
This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220225172021.3493923-19-alex.bennee@linaro.org>
2022-02-28tests/tcg: completely disable threadcount for sh4Alex Bennée
The previous disabling of threadcount 3bdc19af00 ("tests/tcg/sh4: disable another unreliable test") just for plugins was being too conservative. It's all broken so skip it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-17-alex.bennee@linaro.org>
2022-02-28tests/tcg: add vectorised sha512 versionsAlex Bennée
This builds vectorised versions of sha512 to exercise the vector code: - aarch64 (AdvSimd) - i386 (SSE) - s390x (MVX) - ppc64/ppc64le (power10 vectors) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-14-alex.bennee@linaro.org>
2022-02-28tests/tcg: add sha512 testAlex Bennée
This imports the sha512 algorithm and related tests from ccan which offers a cleaner hash implementation with its own validation tests with which we can exercise TCG code generations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-13-alex.bennee@linaro.org>
2022-02-28tests/tcg: build sha1-vector with O3 and compareAlex Bennée
The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and baring compiler bugs the outputs should match. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-12-alex.bennee@linaro.org>
2022-02-28tests/tcg/ppc64: clean-up handling of byte-reverseAlex Bennée
Rather than having an else leg for the missing compiler case we can simply just not add the test - the same way as is done for ppc64le. Also while we are at it fix up the compiler invocation. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-11-alex.bennee@linaro.org>
2022-02-28tests/docker: introduce debian-riscv64-test-crossAlex Bennée
Cross building QEMU for riscv64 still involves messing about with sid and ports. However for building tests we can have a slimmer compiler only container which should be more stable. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-7-alex.bennee@linaro.org>
2022-02-28tests/docker: update debian-arm64-cross with lcitoolAlex Bennée
Using lcitool update debian-arm64-cross to a Debian 11 based system. As a result we can drop debian-arm64-test-cross just for building tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-5-alex.bennee@linaro.org>
2022-02-28tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3David Miller
tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-4-dmiller423@gmail.com> [thuth: Squash mnemonic -> .insn patch, white space cleanup, improve asm usage] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-14Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' ↵Peter Maydell
into staging Fix safe_syscall_base for sparc64. Fix host signal handling for sparc64-linux. Speedups for jump cache and work list probing. Fix for exception replays. Raise guest SIGBUS for user-only misaligned accesses. # gpg: Signature made Fri 11 Feb 2022 01:27:16 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20220211: (34 commits) tests/tcg/multiarch: Add sigbus.c tcg/sparc: Support unaligned access for user-only tcg/sparc: Add tcg_out_jmpl_const for better tail calls tcg/sparc: Use the constant pool for 64-bit constants tcg/sparc: Convert patch_reloc to return bool tcg/sparc: Improve code gen for shifted 32-bit constants tcg/sparc: Add scratch argument to tcg_out_movi_int tcg/sparc: Split out tcg_out_movi_imm32 tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 tcg/mips: Support unaligned access for softmmu tcg/mips: Support unaligned access for user-only tcg/arm: Support raising sigbus for user-only tcg/arm: Reserve a register for guest_base tcg/arm: Support unaligned access for softmmu tcg/arm: Check alignment for ldrd and strd tcg/arm: Remove use_armv6_instructions tcg/arm: Remove use_armv5t_instructions tcg/arm: Drop support for armv4 and armv5 hosts tcg/loongarch64: Support raising sigbus for user-only tcg/tci: Support raising sigbus for user-only ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-09linux-user: Remove the deprecated ppc64abi32 targetThomas Huth
It's likely broken, and nobody cared for picking it up again during the deprecation phase, so let's remove this now. Since this is the last entry in deprecated_targets_list, remove the related code in the configure script, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cédric Le Goater <clg@kaod.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211215084958.185214-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220112112722.3641051-32-alex.bennee@linaro.org>
2022-02-09tests/tcg/sh4: disable another unreliable testAlex Bennée
Given the other failures it looks like general thread handling on sh4 is sketchy. It fails more often on CI than on my developer machine though. See https://gitlab.com/qemu-project/qemu/-/issues/856 for more details. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Laurent Vivier <laurent@vivier.eu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220204204335.1689602-17-alex.bennee@linaro.org>
2022-02-09tests/tcg/multiarch: Add sigbus.cRichard Henderson
A mostly generic test for unaligned access raising SIGBUS. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-19Merge remote-tracking branch ↵Peter Maydell
'remotes/thuth-gitlab/tags/pull-request-2022-01-19' into staging * Fix bits in one of the PMCW channel subsystem masks * s390x TCG shift instruction fixes * Re-organization for the MAINTAINERS file * Support for extended length of kernel command lines * Re-order the SIGP STOP code # gpg: Signature made Wed 19 Jan 2022 08:26:01 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/thuth-gitlab/tags/pull-request-2022-01-19: s390x: sigp: Reorder the SIGP STOP code s390x/ipl: support extended kernel command line size MAINTAINERS: Add myself to s390 I/O areas MAINTAINERS: split out s390x sections tests/tcg/s390x: Test shift instructions target/s390x: Fix shifting 32-bit values for more than 31 bits target/s390x: Fix cc_calc_sla_64() missing overflows target/s390x: Fix SRDA CC calculation target/s390x: Fix SLDA sign bit index s390x/css: fix PMCW invalid mask Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-18test/tcg/ppc64le: Add float reference filesRichard Henderson
Generated on Power9, PowerNV 9006-22P. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211224035541.2159966-3-richard.henderson@linaro.org> Message-Id: <20220105135009.1584676-30-alex.bennee@linaro.org>
2022-01-18tests/tcg/multiarch: Read fp flags before printfRichard Henderson
We need to read the floating-point flags before printf may do other floating-point operations which may affect the flags. Hexagon reference files regenerated by Taylor Simpson. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1639510781-3790-1-git-send-email-tsimpson@quicinc.com> Message-Id: <20211224035541.2159966-2-richard.henderson@linaro.org> Message-Id: <20220105135009.1584676-29-alex.bennee@linaro.org>
2022-01-18tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUXPaolo Bonzini
The two more or less overlap, because CONFIG_LINUX is a requirement for Linux user-mode emulation. However, CONFIG_LINUX is technically a host symbol that applies even to system emulation. Defining CONFIG_LINUX_USER, and CONFIG_BSD_USER for eventual future use, is cleaner. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211210084836.25202-1-pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220105135009.1584676-20-alex.bennee@linaro.org>
2022-01-17tests/tcg/s390x: Test shift instructionsIlya Leoshkevich
Add a test for each shift instruction in order to to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Message-Id: <20220112165016.226996-6-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-12tests/tcg: Fix target-specific Makefile variables path for user-modePhilippe Mathieu-Daudé
Commit 812b31d3f91 refactor missed to update this path. Fixes: 812b31d3f91 ("configs: rename default-configs to configs and reorganise") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211226001541.3807919-1-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer precision insns doesn't silence SNaNs in the hardware. To better match this behavior, use the non-arithmatic conversion of helper_todouble instead of float32_to_float64. A test is added to prevent future regressions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-30target/hppa: Fix atomic_store_3 for STBYRichard Henderson
The parallel version of STBY did not take host endianness into account, and also computed the incorrect address for STBY_E. Bswap twice to handle the merge and store. Compute mask inside the function rather than as a parameter. Force align the address, rather than subtracting one. Generalize the function to system mode by using probe_access(). Cc: qemu-stable@nongnu.org Tested-by: Helge Deller <deller@gmx.de> Reported-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-30tests/tcg: Unconditionally use 90 second timeoutRichard Henderson
The cross-i386-tci test has timeouts because we're no longer applying the timeout that we desired. Hack around it. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Fixes: 23a77b2d18b8 ("build-system: clean up TCG/TCI configury") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-28 21:51:35 +0000