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2023-03-15tests/tcg/xtensa: allow testing big-endian coresMax Filippov
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2023-03-15tests/tcg/xtensa: add linker.ld to CLEANFILESMax Filippov
Linker script for xtensa tests must be preprocessed for a specific target, remove it as a part of make clean. Fixes: be5cac175a ("tests/tcg/xtensa: enable system tests") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-05-06tests/tcg/xtensa: fix vectors and checks in timer testMax Filippov
Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: enable mmu tests for MMUv3Max Filippov
MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses explicit and invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3Max Filippov
Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: remove dependency on the loop optionMax Filippov
xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: fix watchpoint testMax Filippov
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK* registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: restore vecbase SR after testMax Filippov
Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value after the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-05-06tests/tcg/xtensa: fix build for cores without windowed registersMax Filippov
Don't try to initialize windowbase/windowstart in crt.S if they don't exist. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-05-20target/xtensa: clean up unaligned accessMax Filippov
Xtensa cores may or may not have hardware support for unaligned memory access. Remove TARGET_ALIGNED_ONLY=y from all xtensa configurations and pass MO_ALIGN in memory access flags for all operations that would raise an exception. Simplify use of gen_load_store_alignment by passing access size and alignment requirements in single parameter. Drop condition from xtensa_cpu_do_unaligned_access and replace it with assertion. Add a test. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: add DFP0 arithmetic testsMax Filippov
Add test for basic double precision opcode properties. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: test double precision load/storeMax Filippov
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: add fp0 div and sqrt testsMax Filippov
Test exact division/sqrt DFPU sequences. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: update test_lsc for DFPUMax Filippov
DFPU doesn't have pre-increment FP load/store opcodes, it has post-increment opcodes instead. Test increment opcodes present in the current config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: update test_fp1 for DFPUMax Filippov
DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: update test_fp0_conv for DFPUMax Filippov
DFPU conversion opcodes update FSR flags. Add FSR parameters and expected FSR register values for the conversion tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: expand madd testsMax Filippov
Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: update test_fp0_arith for DFPUMax Filippov
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21tests/tcg/xtensa: fix test execution on ISSMax Filippov
Space for test results may be allocated in IRAM which is only word-accessible. Use full 32-bit words to access test results. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-09-10tests/tcg: move configuration to a sub-shell scriptPaolo Bonzini
Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu [AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net>
2019-09-10tests/tcg: use EXTRA_CFLAGS everywherePaolo Bonzini
For i386 specifically, this allows using the host GCC to compile the i386 tests. But, it should really be done for all targets, unless we want to pass $(EXTRA_CFLAGS) directly as part of $(CC). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-2-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-23tests/tcg/xtensa: clean up test setMax Filippov
Drop test_fail: we know that exit simcall works. Now that it's not run automatically there's no point in keeping it. Drop test_pipeline: we're not modeling pipeline, we don't control ccount and there's no plan to do so. Enable test_boolean: it won't break on cores without boolean option, it will do testing on cores with boolean option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-21target/xtensa: fix break_dependency for repeated resourcesMax Filippov
break_dependency incorrectly handles the case of dependency on an opcode that references the same register multiple times. E.g. the following instruction is translated incorrectly: { or a2, a3, a3 ; or a3, a2, a2 } This happens because resource indices of both dependency graph nodes are incremented, and a copy for the second instance of the same register in the ending node is not done. Only increment resource index of the ending node of the dependency. Add test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-12tests/tcg/xtensa: enable system testsAlex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12tests/docker: add debian-xtensa-cross imagePhilippe Mathieu-Daudé
Xtensa cpu supported: - dc232b - dc233c - csp Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-28tests/tcg/xtensa: add FPU2000 coprocessor testsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP1 group testsMax Filippov
Test comparisons and conditional move operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP0 group conversion testsMax Filippov
Test conversions for normal, NaN and Inf arguments. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add FP0 group arithmetic testsMax Filippov
Test arithmetic operations for normal, NaN and Inf arguments. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add LSCI/LSCX group testsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add test for FLIXMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize MMU-related testsMax Filippov
Make MMU-related tests conditional on the presence of MMUv2 option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize windowed register testsMax Filippov
Make windowed register tests conditional on the presence of this option. Fix tests to work correctly for both 32 and 64 physical registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize and fix s32c1i testsMax Filippov
Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: fix SR tests for big endian configsMax Filippov
SR tests generate instructions that the assembler does not recognize and thus must take care about configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize and expand SR testsMax Filippov
Make tests for specific special registers conditional on the presence of the options that add these registers and test that the registers are not accessible otherwise. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize timer/CCOUNT testsMax Filippov
Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize interrupt testsMax Filippov
Make interrupt tests conditional on the presence of interrupt option and on the presence of level-1 and high level software interrupts. Don't use hard-coded interrupt level for the high level interrupt tests, choose high level software IRQ and use its configured level. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: add straightforward conditionalsMax Filippov
Make tests for optional instruction groups conditional on the presence of corresponding options in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize cache option testsMax Filippov
Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: conditionalize debug option testsMax Filippov
Make debug tests conditional on the presence of the debug option in the config and tests that depend on the presence/number of instruction or data breakpoint registers on the corresponding definitions. Use configured debug interrupt level instead of the hardcoded value to set up IRQ handler and access debug EPC register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: enable boolean testsMax Filippov
Uncomment test_boolean in the test makefile. Make actual tests code conditional on the presence of boolean option in the config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: fix endianness issues in test_bMax Filippov
Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that accept little-endian bit number and produce correct immediate for both little and big endian configurations. Choose value loaded into register for bbc/bbs opcodes based on configuration endianness. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: don't use optional opcodes in generic codeMax Filippov
Don't use 'loop' opcode in generic testsuite completion code, only use core opcodes to make it work with any configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: support configs with LITBASEMax Filippov
Configurations with LITBASE register may use absolute literals by default. Pass --no-absolute-literals option to assembler to use PC-relative literals instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: support configurations w/o vecbaseMax Filippov
Configurations w/o vecbase may have vectors not grouped together and not in fixed order. They may not always be grouped into single output sections by assigning next offset to dot, as it may sometimes move dot backwards and sometimes they may even belong to different memory region. Don't group vectors into single output section. Instead put each vector into its own section ant put it at its default virtual address. Reserve 4KBytes from the default vectors base and put rest of the code and data starting from there. Mark vectors sections as executable, otherwise their contents is discarded. There may be as little as 16 bytes reserved for some vectors, load handler address into a0 and use ret.n to jump there to make vector code fit into this 16 byte space. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28tests/tcg/xtensa: indicate failed testsMax Filippov
When test suite with multiple tests fails it's not obvious which test failed. Pring "failed" in every invocation of test_fail. Do printing when DEBUG preprocessor macro is defined. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17tests/tcg/xtensa: only generate defined exception handlersMax Filippov
Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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