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2022-07-31Hexagon (target/hexagon) make VyV operands use a unique tempTaylor Simpson
VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-2-tsimpson@quicinc.com>
2022-03-12Hexagon HVX (target/hexagon) fix bug in HVX saturate instructionsTaylor Simpson
Two tests added to tests/tcg/hexagon/hvx_misc.c v21.uw = vadd(v11.uw, v10.uw):sat v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-3-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-03Hexagon HVX (tests/tcg/hexagon) hvx_misc testTaylor Simpson
Tests for packet semantics vector loads (aligned and unaligned) vector stores (aligned and unaligned) vector masked stores vector new value store maximum HVX temps in a packet vector operations Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>