aboutsummaryrefslogtreecommitdiff
path: root/tests/tcg/aarch64
AgeCommit message (Collapse)Author
2023-11-02tests/tcg: Add -fno-stack-protectorAkihiko Odaki
A build of GCC 13.2 will have stack protector enabled by default if it was configured with --enable-default-ssp option. For such a compiler, it is necessary to explicitly disable stack protector when linking without standard libraries. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20230731091042.139159-3-akihiko.odaki@daynix.com> [AJB: fix comment string typo] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231029145033.592566-3-alex.bennee@linaro.org> (cherry picked from commit 580731dcc87eb27a2b0dc20ec331f1ce51864c97) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2022-10-06tests/tcg: move compiler tests to MakefilesPaolo Bonzini
Further decoupling of tests/tcg from the main QEMU Makefile, and making the build more similar between the cross compiler case and the vetted container images. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-25-alex.bennee@linaro.org>
2022-10-06tests/tcg: clean up calls to run-testPaolo Bonzini
Almost all invocations of run-test have either "$* on $(TARGET_NAME)" or "$< on $(TARGET_NAME)" as the last argument. So provide a default test name, while allowing an escape hatch for custom names. As an additional simplification, remove the need to do shell quoting. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-24-alex.bennee@linaro.org>
2022-07-06tests/tcg: compile system emulation tests as freestandingPaolo Bonzini
System emulation tests do not run in a hosted environment, since they do not link with libc. They should only use freestanding headers (float.h, limits.h, stdarg.h, stddef.h, stdbool.h, stdint.h, stdalign.h, stdnoreturn.h) and should be compiled with -ffreestanding in order to use the compiler implementation of those headers rather than the one in libc. Some tests are using inttypes.h instead of stdint.h, so fix that. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-05target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-userRichard Henderson
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3 (indirect branch from register other than x16/x17). The linux kernel sets this in bti_enable(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220427042312.294300-1-richard.henderson@linaro.org [PMM: remove stray change to makefile comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-20tests/tcg: add float_convd testAlex Bennée
This is a simple transliteration of the float_convs test but this time working with doubles. I'm used it to test the handling of vector registers in gdbstub but wasn't able to find a non-ugly way to automate it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220419091020.3008144-23-alex.bennee@linaro.org>
2022-04-20tests/tcg: add compiler test variables when using containersPaolo Bonzini
Even for container-based cross compilation use $(CROSS_CC_HAS_*) variables. This makes the TCG test makefiles oblivious of whether the compiler is invoked through a container or not. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220401141326.1244422-10-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220419091020.3008144-13-alex.bennee@linaro.org>
2022-03-18target/arm: Fix sve2 ldnt1 and stnt1Richard Henderson
For both ldnt1 and stnt1, the meaning of the Rn and Rm are different from ld1 and st1: the vector and integer registers are reversed, and the integer register 31 refers to XZR instead of SP. Secondly, the 64-bit version of ldnt1 was being interpreted as 32-bit unpacked unscaled offset instead of 64-bit unscaled offset, which discarded the upper 32 bits of the address coming from the vector argument. Thirdly, validate that the memory element size is in range for the vector element size for ldnt1. For ld1, we do this via independent decode patterns, but for ldnt1 we need to do it manually. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220308031655.240710-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28tests/tcg: port SYS_HEAPINFO to a system testAlex Bennée
This allows us to check our new SYS_HEAPINFO implementation generates sane values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220225172021.3493923-19-alex.bennee@linaro.org>
2022-02-28tests/tcg: add vectorised sha512 versionsAlex Bennée
This builds vectorised versions of sha512 to exercise the vector code: - aarch64 (AdvSimd) - i386 (SSE) - s390x (MVX) - ppc64/ppc64le (power10 vectors) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-14-alex.bennee@linaro.org>
2022-02-28tests/tcg: build sha1-vector with O3 and compareAlex Bennée
The aim of this is to test code generation for vectorised operations. Unfortunately gcc struggles to do much with the messy sha1 code (try -fopt-info-vec-missed to see why). However it's better than nothing. We assume the non-vectorised output is gold and baring compiler bugs the outputs should match. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225172021.3493923-12-alex.bennee@linaro.org>
2021-12-15tests/tcg: Add arm and aarch64 pc alignment testsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-16target/arm: Fix mte page crossing testRichard Henderson
The test was off-by-one, because tag_last points to the last byte of the tag to check, thus tag_last - prev_page will equal TARGET_PAGE_SIZE when we use the first byte of the next page. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403 Reported-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210612195707.840217-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30test/tcg/aarch64: Add mte-5Richard Henderson
Buglink: https://bugs.launchpad.net/bugs/1921948 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-12accel/tcg: Preserve PAGE_ANON when changing page permissionsRichard Henderson
Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-24semihosting: move semihosting tests to multiarchAlex Bennée
It may be arm-compat-semihosting but more than one architecture uses it so lets move the tests into the multiarch area. We gate it on the feature and split the semicall.h header between the arches. Also clean-up a bit of the Makefile messing about to one common set of runners. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323165308.15244-6-alex.bennee@linaro.org>
2021-02-16tests/tcg/aarch64: Add mte smoke testsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-16target/arm: Use the proper TBI settings for linux-userRichard Henderson
We were fudging TBI1 enabled to speed up the generated code. Now that we've improved the code generation, remove this. Also, tidy the comment to reflect the current code. The pauth test was testing a kernel address (-1) and making incorrect assumptions about TBI1; stick to userland addresses. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Machado <luis.machado@linaro.org> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org>
2021-01-18gdbstub: implement a softmmu based testAlex Bennée
This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to: - add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org>
2020-10-27tests/tcg/aarch64: Add bti smoke testsRichard Henderson
The note test requires gcc 10 for -mbranch-protection=standard. The mmap test uses PROT_BTI and does not require special compiler support. Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201021173749.111103-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Fix AddPAC error indicationRichard Henderson
The definition of top_bit used in this function is one higher than that used in the Arm ARM psuedo-code, which put the error indication at top_bit - 1 at the wrong place, which meant that it wasn't visible to Auth. Fixing the definition of top_bit requires more changes, because its most common use is for the count of bits in top_bit:bot_bit, which would then need to be computed as top_bit - bot_bit + 1. For now, prefer the minimal fix to the error indication alone. Fixes: 63ff0ca94cb Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200728195706.11087-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added comment about the divergence from the pseudocode] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-16tests/tcg: ensure -cpu max also used for plugin runAlex Bennée
The check-tcg plugins build was failing because some special case tests that needed -cpu max failed because the plugin variant hadn't carried across the QEMU_OPTS tweak. Guests which globally set QEMU_OPTS=-cpu FOO where unaffected. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-3-alex.bennee@linaro.org>
2020-06-16tests/tcg: build plugin list from contents of src directoryAlex Bennée
If you jump back and forth between branches while developing plugins you end up debugging failures caused by plugins left in the build directory. Fix this by basing plugins on the source tree instead. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-2-alex.bennee@linaro.org>
2020-05-27tests/tcg: fix invocation of the memory record/replay testsAlex Bennée
I'm not sure when this broke but we should use EXTRA_RUNS for "virtual" tests which are not generated from the binary names. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200520140541.30256-5-alex.bennee@linaro.org>
2020-05-06tests/tcg: add a multiarch linux-user gdb testAlex Bennée
When the gdbstub code was converted to the new API we missed a few snafus in the various guests. Add a simple gdb test script which can be used on all our linux-user guests to check for obvious failures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200430190122.4592-9-alex.bennee@linaro.org>
2020-05-06tests/tcg: drop inferior.was_attached() testAlex Bennée
This test seems flaky and reports attachment even when we failed to negotiate the architecture. However the fetching of the guest architecture will fail tripping up the gdb AttributeError which will trigger our early no error status exit from the test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200430190122.4592-5-alex.bennee@linaro.org>
2020-05-06tests/tcg: better trap gdb failuresAlex Bennée
It seems older and non-multiarach aware GDBs might not fail gracefully when faced with something they don't know. For example when faced with a target XML for s390x the Ubuntu 18.04 gdb will generate an internal fault and prompt for a core dump. Work around this by invoking GDB in a more batch orientated way and then trying to filter out between test failures and gdb failures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200430190122.4592-4-alex.bennee@linaro.org>
2020-03-17tests/tcg/aarch64: add test-sve-ioctl guest-debug testAlex Bennée
This test exercises the gdbstub while runing the sve-iotcl test. I haven't plubmed it into make system as we need a way of verifying if gdb has the right support for SVE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200316172155.971-26-alex.bennee@linaro.org>
2020-03-17tests/tcg/aarch64: add SVE iotcl testAlex Bennée
This is a fairly bare-bones test of setting the various vector sizes for SVE which will only fail if the PR_SVE_SET_VL can't reduce the user-space vector length by powers of 2. However we will also be able to use it in a future test which exercises the GDB stub. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200316172155.971-25-alex.bennee@linaro.org>
2020-03-17tests/tcg/aarch64: add a gdbstub testcase for SVE registersAlex Bennée
A very simple test case which sets and reads SVE registers while running a test case. We don't really need to compile a SVE binary for this case but we will later so keep it simple for now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200316172155.971-24-alex.bennee@linaro.org>
2020-03-17tests/tcg/aarch64: userspace system register testAlex Bennée
This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. We need a SVE aware compiler as we are testing the id_aa64zfr0_el1 register in the set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200316172155.971-21-alex.bennee@linaro.org>
2020-03-05tests/tcg/aarch64: Add newline in pauth-1 printfRichard Henderson
Make the output just a bit prettier when running by hand. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-25tests/tcg: take into account expected clashes pauth-4Alex Bennée
Pointer authentication isn't perfect so measure the percentage of failed checks. As we want to vary the pointer we work through a bunch of different addresses. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Robert Foley <robert.foley@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200225124710.14152-20-alex.bennee@linaro.org>
2020-02-25tests/tcg: include a skip runner for pauth3 with pluginsAlex Bennée
If we have plugins enabled we still need to have built the test to be able to run it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Robert Foley <robert.foley@linaro.org> Message-Id: <20200225124710.14152-2-alex.bennee@linaro.org>
2020-02-04tests/tcg: gate pauth-% tests on having compiler supportAlex Bennée
Otherwise we end up failing to build our tests on CI which may have older compilers that the user expects. We can get rid of this once we can fallback to multiarch containers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200203090932.19147-14-alex.bennee@linaro.org>
2020-01-23tests/tcg/aarch64: Add pauth-4Richard Henderson
Perform the set of operations and test described in LP 1859713. Suggested-by: Adrien GRASSEIN <adrien.grassein@smile.fr> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200116230809.19078-5-richard.henderson@linaro.org [PMM: fixed hard-coded tabs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-23tests/tcg/aarch64: Add pauth-3Richard Henderson
This is the test vector from the QARMA paper, run through PACGA. Suggested-by: Vincent Dehors <vincent.dehors@smile.fr> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200116230809.19078-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-23tests/tcg/aarch64: Fix compilation parameters for pauth-%Richard Henderson
We were incorrectly requiring ARMv8.4 support for the pauth tests, but Pointer Authentication is an ARMv8.3 extension. Further, hiding the required architecture within asm() is not correct. Correct the architecture version requested, and specify it in the cflags of the (cross-) compiler rather than in the asm. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200116230809.19078-3-richard.henderson@linaro.org [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-09tests/tcg: add user version of dumb-as-bricks semiconsole testAlex Bennée
There are linux-user users of semihosting so we'd better check things work for them as well. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-01-09tests/tcg: add a dumb-as-bricks semihosting console testAlex Bennée
We don't run this during check-tcg as we would need to check stuff is echoed back. However we can still build the binary so people can test it manually. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28tests/tcg: enable plugin testingAlex Bennée
If CONFIG_PLUGINS is enabled then lets enable testing for all our TCG targets. This is a simple smoke test that ensure we don't crash or otherwise barf out by running each plugin against each test. There is a minor knock on effect for additional runners which need specialised QEMU_OPTS which will also need to declare a plugin version of the runner. If this gets onerous we might need to add another helper. Checking the results of the plugins is left for a later exercise. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28tests/tcg: move "virtual" tests to EXTRA_TESTSAlex Bennée
Otherwise clever expanders like the plugins test get unstuck. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-09-30Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190927' into staging target-arm queue: * Fix the CBAR register implementation for Cortex-A53, Cortex-A57, Cortex-A72 * Fix direct booting of Linux kernels on emulated CPUs which have an AArch32 EL3 (incorrect NSACR settings meant they could not access the FPU) * semihosting cleanup: do more work at translate time and less work at runtime # gpg: Signature made Fri 27 Sep 2019 15:32:43 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190927: hw/arm/boot: Use the IEC binary prefix definitions hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots tests/tcg: add linux-user semihosting smoke test for ARM target/arm: remove run-time semihosting checks for linux-user target/arm: remove run time semihosting checks target/arm: handle A-profile semihosting at translate time target/arm: handle M-profile semihosting at translate time tests/tcg: clean-up some comments after the de-tangling target/arm: fix CBAR register for AArch64 CPUs Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # tests/tcg/arm/Makefile.target
2019-09-27tests/tcg: add linux-user semihosting smoke test for ARMAlex Bennée
We already use semihosting for the system stuff so this is a simple smoke test to ensure we are working OK on linux-user. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190913151845.12582-7-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-27tests/tcg: clean-up some comments after the de-tanglingAlex Bennée
These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190913151845.12582-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-26tests/tcg: add simple record/replay smoke test for aarch64Alex Bennée
This adds two new tests that re-use the memory test to check basic record replay functionality is still working. We have to define our own runners rather than using the default pattern as we want to change the test name but re-use the memory binary. We declare the test binaries as PHONY as they don't really exist. [AJB: A better test would output some sort of timer value or other otherwise variable value so we could compare the record and replay outputs and ensure they match] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Pavel Dovgalyuk <dovgaluk@ispras.ru>
2019-09-26tests/tcg: add generic version of float_convsAlex Bennée
This is broadly similar to the existing fcvt test for ARM but using the generic float testing framework. We should be able to pare down the ARM fcvt test case to purely half-precision with or without the Alt HP provision. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26tests/tcg: add float_madds test to multiarchAlex Bennée
This is a generic floating point multiply and accumulate test for single precision floating point values. I've split of the common float functions into a helper library so additional tests can use the same common code. As I don't have references for all architectures I've allowed some flexibility for tests to pass without reference files. They can be added as we get collect them. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26tests/tcg: clean-up some comments after the de-tanglingAlex Bennée
These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 23:45:54 +0000