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2021-12-18tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521Philippe Mathieu-Daudé
Without the previous commit, this test triggers: $ make check-qtest-x86_64 [...] Running test qtest-x86_64/fuzz-megasas-test qemu-system-x86_64: softmmu/physmem.c:3229: address_space_unmap: Assertion `mr != NULL' failed. Broken pipe ERROR qtest-x86_64/fuzz-megasas-test - too few tests run (expected 2, got 1) Suggested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-Id: <20211119201141.532377-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-12-17Merge tag 'trivial-branch-for-7.0-pull-request' of ↵Richard Henderson
https://gitlab.com/laurent_vivier/qemu into staging Trivial patches pull request 20211217 # gpg: Signature made Fri 17 Dec 2021 12:09:51 PM PST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [unknown] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [unknown] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu: checkpatch: Do not allow deprecated g_memdup() tests/qtest: Replace g_memdup() by g_memdup2() glib-compat: Introduce g_memdup2() wrapper docs/block-replication.txt: Fix replication top-id command demo hw/virtio/vhost: Fix typo in comment. hw/avr: Realize AVRCPU qdev object using qdev_realize() qemu-keymap: Add license in generated files target/i386/kvm: Replace use of __u32 type configure: Symlink binaries using .exe suffix with MinGW Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-17Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into stagingRichard Henderson
ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) # gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits) ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Drop the "num-phbs" property ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Introduce a "chip" property under PHB3 PPC64/TCG: Implement 'rfebb' instruction target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: enable PMU instruction count target/ppc: enable PMU counter overflow with cycle events target/ppc: PMU: update counters on MMCR1 write target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU basic cycle count for pseries TCG ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-17ivshmem-test.c: enable test_ivshmem_server for ppc64 archDaniel Henrique Barboza
This test, if enabled by hand, was failing when the ivhsmem device was being declared as DEVICE_NATIVE_ENDIAN with the following error: /ppc64/ivshmem/pair: OK /ppc64/ivshmem/server: ** ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server: assertion failed (ret != 0): (0 != 0) Aborted After the endianness change done in the previous patch, we can verify in both a a Power 9 little-endian host and in a Power 8 big-endian host that this test is now passing: $ QTEST_QEMU_BINARY=./ppc64-softmmu/qemu-system-ppc64 ./tests/qtest/ivshmem-test -m slow /ppc64/ivshmem/single: OK /ppc64/ivshmem/hotplug: OK /ppc64/ivshmem/memdev: OK /ppc64/ivshmem/pair: OK /ppc64/ivshmem/server: OK Let's keep it that way by officially enabling it for ppc64. Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211124092948.335389-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17tests/qtest: Replace g_memdup() by g_memdup2()Philippe Mathieu-Daudé
Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize to g_memdup(). For large values, that would lead to a silent truncation of the size from 64 to 32 bits, and result in a heap area being returned which is significantly smaller than what the caller expects. This can likely be exploited in various modules to cause a heap buffer overflow. Replace g_memdup() by the safer g_memdup2() wrapper. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903174510.751630-25-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-12-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* improve compatibility for macOS scripts/entitlement.sh (Evan) * add support for KVM_GUESTDBG_BLOCKIRQ (Maxim) * update linux-headers to Linux 5.16 (myself) * configure cleanups (myself) * lsi53c895a assertion failure fix (Philippe) * fix incorrect description for die-id (Yanan) * support for NUMA in SGX enclave memory (Yang Zhong) # gpg: Signature made Wed 15 Dec 2021 02:49:44 AM PST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [unknown] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: configure: remove dead variables doc: Add the SGX numa description numa: Support SGX numa in the monitor and Libvirt interfaces numa: Enable numa for SGX EPC sections kvm: add support for KVM_GUESTDBG_BLOCKIRQ gdbstub, kvm: let KVM report supported singlestep flags gdbstub: reject unsupported flags in handle_set_qemu_sstep linux-headers: update to 5.16-rc1 virtio-gpu: do not byteswap padding scripts/entitlement.sh: Use backward-compatible cp flags qapi/machine.json: Fix incorrect description for die-id tests/qtest: Add fuzz-lsi53c895a-test hw/scsi/lsi53c895a: Do not abort when DMA requested and no data queued Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-16tests/qtest/bios-tables-test: Only run VIOT test on TCGJean-Philippe Brucker
The VIOT test does not always work under KVM on the virt machine: PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Broken pipe Make it TCG only. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-15Merge tag 'pull-target-arm-20211215' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * ITS: error reporting cleanup * aspeed: improve documentation * Fix STM32F2XX USART data register readout * allow emulated GICv3 to be disabled in non-TCG builds * fix exception priority for singlestep, misaligned PC, bp, etc * Correct calculation of tlb range invalidate length * npcm7xx_emc: fix missing queue_flush * virt: Add VIOT ACPI table for virtio-iommu * target/i386: Use assert() to sanity-check b1 in SSE decode * Don't include qemu-common unnecessarily # gpg: Signature made Wed 15 Dec 2021 02:39:37 AM PST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20211215' of https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits) tests/acpi: add expected blob for VIOT test on virt machine tests/acpi: add expected blobs for VIOT test on q35 machine tests/acpi: add test case for VIOT tests/acpi: allow updates of VIOT expected data files hw/arm/virt: Use object_property_set instead of qdev_prop_set hw/arm/virt: Reject instantiation of multiple IOMMUs hw/arm/virt: Remove device tree restriction for virtio-iommu hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu hw/net: npcm7xx_emc fix missing queue_flush target/arm: Correct calculation of tlb range invalidate length hw/arm: Don't include qemu-common.h unnecessarily target/rx/cpu.h: Don't include qemu-common.h target/hexagon/cpu.h: don't include qemu-common.h include/hw/i386: Don't include qemu-common.h in .h files target/i386: Use assert() to sanity-check b1 in SSE decode tests/tcg: Add arm and aarch64 pc alignment tests target/arm: Suppress bp for exceptions with more priority target/arm: Assert thumb pc is aligned target/arm: Take an exception if PC is misaligned target/arm: Split compute_fsr_fsc out of arm_deliver_fault ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-15tests/acpi: add expected blob for VIOT test on virt machineJean-Philippe Brucker
The VIOT blob contains the following: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000058 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 66 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0002 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0008 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00000000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 0000 [04Eh 0078 2] PCI BDF end : 00FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 Acked-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20211210170415.583179-9-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15tests/acpi: add expected blobs for VIOT test on q35 machineJean-Philippe Brucker
Add expected blobs of the VIOT and DSDT table for the VIOT test on the q35 machine. Since the test instantiates a virtio device and two PCIe expander bridges, DSDT.viot has more blocks than the base DSDT. The VIOT table generated for the q35 test is: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000070 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3D [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0003 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0010 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00003000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 3000 [04Eh 0078 2] PCI BDF end : 30FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 [058h 0088 1] Type : 01 [PCI Range] [059h 0089 1] Reserved : 00 [05Ah 0090 2] Length : 0018 [05Ch 0092 4] Endpoint start : 00001000 [060h 0096 2] PCI Segment start : 0000 [062h 0098 2] PCI Segment end : 0000 [064h 0100 2] PCI BDF start : 1000 [066h 0102 2] PCI BDF end : 10FF [068h 0104 2] Output node : 0030 [06Ah 0106 6] Reserved : 000000000000 And the DSDT diff is: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x000024B6 (9398) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFA + * Checksum 0xA7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -3114,6 +3114,339 @@ } } + Scope (\_SB) + { + Device (PC30) + { + Name (_UID, 0x30) // _UID: Unique ID + Name (_BBN, 0x30) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0030, // Range Minimum + 0x0030, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC20) + { + Name (_UID, 0x20) // _UID: Unique ID + Name (_BBN, 0x20) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0020, // Range Minimum + 0x0020, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC10) + { + Name (_UID, 0x10) // _UID: Unique ID + Name (_BBN, 0x10) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0010, // Range Minimum + 0x0010, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + Scope (\_SB.PCI0) { Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings @@ -3121,9 +3454,9 @@ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x000F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0010, // Length ,, ) IO (Decode16, 0x0CF8, // Range Minimum @@ -3278,6 +3611,26 @@ } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + } + + Device (S20) + { + Name (_ADR, 0x00040000) // _ADR: Address + } + + Device (S28) + { + Name (_ADR, 0x00050000) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20211210170415.583179-8-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15tests/acpi: add test case for VIOTJean-Philippe Brucker
Add two test cases for VIOT, one on the q35 machine and the other on virt. To test complex topologies the q35 test has two PCIe buses that bypass the IOMMU (and are therefore not described by VIOT), and two buses that are translated by virtio-iommu. Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20211210170415.583179-7-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15tests/acpi: allow updates of VIOT expected data filesJean-Philippe Brucker
Create empty data files and allow updates for the upcoming VIOT tests. Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20211210170415.583179-6-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15tests: qtest: Add virtio-iommu testEric Auger
Add the framework to test the virtio-iommu-pci device and tests exercising the attach/detach, map/unmap API. Signed-off-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211127072910.1261824-5-eric.auger@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/qtest: Add a function to check whether a machine is availableThomas Huth
It is nowadays possible to build QEMU with a reduced set of machines in each binary. However, the qtests still hard-code the expected machines and fail if the binary does not feature the required machine. Let's get a little bit more flexible here: Add a function that can be used to query whether a certain machine is available or not, and use it in some tests as an example (more work has to be done in other tests which will follow later). Message-Id: <20211201104347.51922-5-thuth@redhat.com> Acked-by: John Snow <jsnow@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/qtest: Add a function that gets a list with available machine typesThomas Huth
For the upcoming patches, we will need a way to gets a list with all available machine types. Refactor the qtest_cb_for_every_machine() to split the related code out into a separate new function, and gather the aliases of the various machine types, too. Message-Id: <20211201104347.51922-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/qtest: Fence the tests that need xlnx-zcu102 with CONFIG_XLNX_ZYNQMP_ARMThomas Huth
The 'xlnx-can-test' and the 'fuzz-xlnx-dp-test' need the "xlnx-zcu102" machine and thus should only be built and run if CONFIG_XLNX_ZYNQMP_ARM is enabled. Message-Id: <20211201104347.51922-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/qtest: Run the PPC 32-bit tests with the 64-bit target binary, tooThomas Huth
The ppc64 target is a superset of the 32-bit target, so we should include the tests here, too. This used to be done in the past already, but it got lost during the conversion to meson. Fixes: a2ce7dbd91 ("meson: convert tests/qtest to meson") Message-Id: <20211201104347.51922-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/libqtest: add a migration test with two couples of failover devicesLaurent Vivier
Signed-off-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211208130350.10178-5-lvivier@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/libqtest: add some virtio-net failover migration cancelling testsLaurent Vivier
Add some tests to check the state of the machine if the migration is cancelled while we are using virtio-net failover. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211208130350.10178-4-lvivier@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15tests/qtest: add some tests for virtio-net failoverLaurent Vivier
Add test cases to test several error cases that must be generated by invalid failover configuration. Add a combination of coldplug and hotplug test cases to be sure the primary is correctly managed according the presence or not of the STANDBY feature. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20211208130350.10178-3-lvivier@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-15qtest/libqos: add a function to initialize secondary PCI busesLaurent Vivier
Scan the PCI devices to find bridge and set PCI_SECONDARY_BUS and PCI_SUBORDINATE_BUS (algorithm from seabios) Signed-off-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211208130350.10178-2-lvivier@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-12-02tests/qtest/fdc-test: Add a regression test for CVE-2021-20196Philippe Mathieu-Daudé
Without the previous commit, when running 'make check-qtest-i386' with QEMU configured with '--enable-sanitizers' we get: AddressSanitizer:DEADLYSIGNAL ================================================================= ==287878==ERROR: AddressSanitizer: SEGV on unknown address 0x000000000344 ==287878==The signal is caused by a WRITE memory access. ==287878==Hint: address points to the zero page. #0 0x564b2e5bac27 in blk_inc_in_flight block/block-backend.c:1346:5 #1 0x564b2e5bb228 in blk_pwritev_part block/block-backend.c:1317:5 #2 0x564b2e5bcd57 in blk_pwrite block/block-backend.c:1498:11 #3 0x564b2ca1cdd3 in fdctrl_write_data hw/block/fdc.c:2221:17 #4 0x564b2ca1b2f7 in fdctrl_write hw/block/fdc.c:829:9 #5 0x564b2dc49503 in portio_write softmmu/ioport.c:201:9 Add the reproducer for CVE-2021-20196. Suggested-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20211124161536.631563-4-philmd@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2021-11-30tests/qtest: Add fuzz-lsi53c895a-testPhilippe Mathieu-Daudé
Without the previous commit, this test triggers: $ make check-qtest-x86_64 [...] Running test qtest-x86_64/fuzz-lsi53c895a-test qemu-system-x86_64: hw/scsi/lsi53c895a.c:624: lsi_do_dma: Assertion `s->current' failed. ERROR qtest-x86_64/fuzz-lsi53c895a-test - too few tests run (expected 1, got 0) Suggested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20211123111732.83137-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-19qtest/am53c974-test: add test for reset before transferMark Cave-Ayland
Based upon the qtest reproducer posted to Gitlab issue #724 at https://gitlab.com/qemu-project/qemu/-/issues/724. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211118100327.29061-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-09tests/qtest/virtio-net: fix hotplug test caseLaurent Vivier
virtio-net-test has an hotplug testcase that is never executed. This is because the testcase is attached to virtio-pci interface rather than to virtio-net-pci. $ QTEST_QEMU_BINARY=./qemu-system-x86_64 tests/qtest/qos-test -l | grep hotplug /x86_64/.../pci-ohci-tests/ohci_pci-test-hotplug /x86_64/.../e1000e/e1000e-tests/hotplug /x86_64/.../virtio-blk-pci/virtio-blk-pci-tests/hotplug /x86_64/.../vhost-user-blk-pci/vhost-user-blk-pci-tests/hotplug /x86_64/.../virtio-rng-pci/virtio-rng-pci-tests/hotplug /x86_64/.../virtio-scsi/virtio-scsi-tests/hotplug /x86_64/.../virtio-serial/virtio-serial-tests/hotplug With this fix: $ QTEST_QEMU_BINARY=./qemu-system-x86_64 tests/qtest/qos-test -l | grep hotplug ... /x86_64/.../vhost-user-blk-pci/vhost-user-blk-pci-tests/hotplug /x86_64/.../virtio-net-pci/virtio-net-pci-tests/hotplug /x86_64/.../virtio-rng-pci/virtio-rng-pci-tests/hotplug ... $ QTEST_QEMU_BINARY=./qemu-system-x86_64 tests/qtest/qos-test -p /x86_64/.../virtio-net-pci-tests/hotplug /x86_64/pc/i440FX-pcihost/pci-bus-pc/pci-bus/virtio-net-pci/virtio-net-pci-tests/hotplug: OK Fixes: 6ae333f91b99 ("qos-test: virtio-net test node") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211028173014.139692-1-lvivier@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-11-03Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingRichard Henderson
* Build system fixes and cleanups * DMA support in the multiboot option ROM * Rename default-bus-bypass-iommu * Deprecate -watchdog and cleanup -watchdog-action * HVF fix for <PAGE_SIZE regions * Support TSC scaling for AMD nested virtualization * Fix for ESP fuzzing bug # gpg: Signature made Tue 02 Nov 2021 10:57:37 AM EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * remotes/bonzini/tags/for-upstream: (27 commits) configure: fix --audio-drv-list help message configure: Remove the check for the __thread keyword Move the l2tpv3 test from configure to meson.build meson: remove unnecessary coreaudio test program meson: remove pointless warnings meson.build: Allow to disable OSS again meson: bump submodule to 0.59.3 qtest/am53c974-test: add test for cancelling in-flight requests esp: ensure in-flight SCSI requests are always cancelled KVM: SVM: add migration support for nested TSC scaling hw/i386: fix vmmouse registration watchdog: remove select_watchdog_action vl: deprecate -watchdog watchdog: add information from -watchdog help to -device help hw/i386: Rename default_bus_bypass_iommu hvf: Avoid mapping regions < PAGE_SIZE as ram configure: do not duplicate CPU_CFLAGS into QEMU_LDFLAGS configure: remove useless NPTL probe target/i386: use DMA-enabled multiboot ROM for new-enough QEMU machine types optionrom: add a DMA-enabled multiboot ROM ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-03Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211102-2' into stagingRichard Henderson
Add nuvoton sd module for NPCM7XX Add gdb-xml for MVE More uses of tcg_constant_* in target/arm Fix parameter naming for default-bus-bypass-iommu Ignore cache operations to mmio in HVF # gpg: Signature made Tue 02 Nov 2021 02:23:53 PM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-arm-20211102-2: hvf: arm: Ignore cache operations on MMIO hw/arm/virt: Rename default_bus_bypass_iommu target/arm: Use tcg_constant_i32() in gen_rev16() target/arm: Use tcg_constant_i64() in do_sat_addsub_64() target/arm: Use the constant variant of store_cpu_field() when possible target/arm: Introduce store_cpu_field_constant() helper target/arm: Use tcg_constant_i32() in op_smlad() target/arm: Advertise MVE to gdb when present tests/qtest/libqos: add SDHCI commands hw/arm: Attach MMC to quanta-gbs-bmc hw/arm: Add Nuvoton SD module to board hw/sd: add nuvoton MMC Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02tests/qtest/libqos: add SDHCI commandsShengtan Mao
Signed-off-by: Shengtan Mao <stmao@google.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Chris Rauer <crauer@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20211008002628.1958285-5-wuhaotsh@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02qapi: introduce x-query-opcount QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info opcount" command. It is being added with an "x-" prefix because this QMP command is intended as an ad hoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02qapi: introduce x-query-jit QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info jit" command. It is being added with an "x-" prefix because this QMP command is intended as an ad hoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02qapi: introduce x-query-usb QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info usb" command. It is being added with an "x-" prefix because this QMP command is intended as an adhoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02qapi: introduce x-query-profile QMP commandDaniel P. Berrangé
This is a counterpart to the HMP "info profile" command. It is being added with an "x-" prefix because this QMP command is intended as an adhoc debugging tool and will thus not be modelled in QAPI as fully structured data, nor will it have long term guaranteed stability. The existing HMP command is rewritten to call the QMP command. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2021-11-02qtest/am53c974-test: add test for cancelling in-flight requestsMark Cave-Ayland
Based upon the qtest reproducer posted to Gitlab issue #663 at https://gitlab.com/qemu-project/qemu/-/issues/663. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20211101183516.8455-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-10-20tests/acpi/bios-tables-test: update DSDT blob for multifunction bridge testAni Sinha
We added a new unit test for testing acpi hotplug on multifunction bridges in q35 machines. Here, we update the DSDT table gloden master blob for this unit test. The test adds the following devices to qemu and then checks the changes introduced in the DSDT table due to the addition of the following devices: (a) a multifunction bridge device (b) a bridge device with function 1 (c) a non-bridge device with function 2 In the DSDT table, we should see AML hotplug descriptions for (a) and (b). For (a) we should find a hotplug AML description for function 0. Following is the ASL diff between the original DSDT table and the modified DSDT table due to the unit test. We see that multifunction bridge on bus 2 and single function bridge on bus 3 function 1 are described, not the non-bridge balloon device on bus 4, function 2. @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20190509 (64-bit version) * Copyright (c) 2000 - 2019 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Thu Oct 7 18:29:19 2021 + * Disassembly of /tmp/aml-C7JCA1, Thu Oct 7 18:29:19 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x00002187 (8583) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xF9 + * Checksum 0x8D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -3265,23 +3265,95 @@ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State { Return (Zero) } Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State { Return (Zero) } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (Zero) } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name (BSEL, One) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = One + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + + Device (S19) + { + Name (_ADR, 0x00030001) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + Method (PCNT, 0, NotSerialized) { + ^S19.PCNT () + ^S10.PCNT () } } } } Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20211007135750.1277213-4-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com>
2021-10-20tests/acpi/pcihp: add unit tests for hotplug on multifunction bridges for q35Ani Sinha
commit d7346e614f4ec ("acpi: x86: pcihp: add support hotplug on multifunction bridges") added ACPI hotplug descriptions for cold plugged bridges for functions other than 0. For all other devices, the ACPI hotplug descriptions are limited to function 0 only. This change adds unit tests for this feature. This test adds the following devices to qemu and then checks the changes introduced in the DSDT table due to the addition of the following devices: (a) a multifunction bridge device (b) a bridge device with function 1 (c) a non-bridge device with function 2 In the DSDT table, we should see AML hotplug descriptions for (a) and (b). For (a) we should find a hotplug AML description for function 0. The following diff compares the DSDT table AML with the new unit test before and after the change d7346e614f4ec is introduced. In other words, this diff reflects the changes that occurs in the DSDT table due to the change d7346e614f4ec . @@ -1,60 +1,38 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20190509 (64-bit version) * Copyright (c) 2000 - 2019 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT.multi-bridge, Thu Oct 7 18:56:05 2021 + * Disassembly of /tmp/aml-AN0DA1, Thu Oct 7 18:56:05 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x000020FE (8446) + * Length 0x00002187 (8583) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xDE + * Checksum 0x8D * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { - /* - * iASL Warning: There was 1 external control method found during - * disassembly, but only 0 were resolved (1 unresolved). Additional - * ACPI tables may be required to properly disassemble the code. This - * resulting disassembler output file may not compile because the - * disassembler did not know how many arguments to assign to the - * unresolved methods. Note: SSDTs can be dynamically loaded at - * runtime and may or may not be available via the host OS. - * - * In addition, the -fe option can be used to specify a file containing - * control method external declarations with the associated method - * argument counts. Each line of the file must be of the form: - * External (<method pathname>, MethodObj, <argument count>) - * Invocation: - * iasl -fe refs.txt -d dsdt.aml - * - * The following methods were unresolved and many not compile properly - * because the disassembler had to guess at the number of arguments - * required for each: - */ - External (_SB_.PCI0.S19_.PCNT, MethodObj) // Warning: Unknown method, guessing 1 arguments - Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } Method (DBUG, 1, NotSerialized) { ToHexString (Arg0, Local0) ToBuffer (Local0, Local0) Local1 = (SizeOf (Local0) - One) Local2 = Zero While ((Local2 < Local1)) { @@ -3322,24 +3300,60 @@ Method (DVNT, 2, NotSerialized) { If ((Arg0 & One)) { Notify (S00, Arg1) } } Method (PCNT, 0, NotSerialized) { BNUM = One DVNT (PCIU, One) DVNT (PCID, 0x03) } } + Device (S19) + { + Name (_ADR, 0x00030001) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + Method (PCNT, 0, NotSerialized) { - ^S19.PCNT (^S10.PCNT ()) + ^S19.PCNT () + ^S10.PCNT () } } } } Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20211007135750.1277213-3-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2021-10-20tests/acpi/bios-tables-test: add and allow changes to a new q35 DSDT table blobAni Sinha
We are adding a new unit test to cover the acpi hotplug support in q35 for multi-function bridges. This test uses a new table DSDT.multi-bridge. We need to allow changes in DSDT acpi table for addition of this new unit test. Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20211007135750.1277213-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com>
2021-10-20bios-tables-test: don't disassemble empty filesMichael S. Tsirkin
A recommended way to populate new tables is to have an empty expected file. In this case, attempts to disassemble will fail but it is useful to disassemble the actual files. Detect and skip decompile step in this case. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20vhost-user-blk-test: pass vhost-user socket fds to QSDStefan Hajnoczi
qemu-storage-daemon is launched with the vhost-user listen socket path. The path is first unlinked before opening the listen socket. This prevents stale UNIX domain socket files from stopping socket initialization. This behavior is undesirable in vhost-user-blk-test and the cause of a bug: There is a race condition in vhost-user-blk-test when QEMU launches before QSD. It connects to the old socket that QSD unlinks and the vhost-user connection is never serviced, resulting in a hang. Pass the listen socket fd to QSD to maintain listen socket continuity and prevent the lost connection. Fixes: 806952026df41939680abe92b329715b9b4e01cc ("test: new qTest case to test the vhost-user-blk-server") Cc: Raphael Norwitz <raphael.norwitz@nutanix.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Coiby Xu <coiby.xu@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20211019135655.83067-1-stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: bios-tables-test: use qtest_has_accel() API to register TCG only testsIgor Mammedov
.. only if TCG is available Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-16-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: migration-test: use qtest_has_accel() APIIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Suggested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210902113551.461632-15-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: arm-cpu-features: use qtest_has_kvm() APIIgor Mammedov
and drop custom function that were doing the job Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-14-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: arm/virt: drop redundant test_acpi_one() in test_acpi_virt_tcg()Igor Mammedov
follow up call with smbios options generates the same ACPI tables, so there is no need to run smbios-less variant at all. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-13-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: update expected blobsIgor Mammedov
DSDT: + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } New IVRS table: [000h 0000 4] Signature : "IVRS" [I/O Virtualization Reporting Structure] [004h 0004 4] Table Length : 00000068 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 43 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Virtualization Info : 00002800 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Subtable Type : 10 [Hardware Definition Block] [031h 0049 1] Flags : D1 [032h 0050 2] Length : 0038 [034h 0052 2] DeviceId : 0010 [036h 0054 2] Capability Offset : 0040 [038h 0056 8] Base Address : 00000000FED80000 [040h 0064 2] PCI Segment Group : 0000 [042h 0066 2] Virtualization Info : 0000 [044h 0068 4] Reserved : 00000044 [048h 0072 1] Entry Type : 02 [049h 0073 2] Device ID : 0000 [04Bh 0075 1] Data Setting : 00 [04Ch 0076 1] Entry Type : 02 [04Dh 0077 2] Device ID : 0008 [04Fh 0079 1] Data Setting : 00 [050h 0080 1] Entry Type : 02 [051h 0081 2] Device ID : 0010 [053h 0083 1] Data Setting : 00 [054h 0084 1] Entry Type : 02 [055h 0085 2] Device ID : 00F8 [057h 0087 1] Data Setting : 00 [058h 0088 1] Entry Type : 02 [059h 0089 2] Device ID : 00FA [05Bh 0091 1] Data Setting : 00 [05Ch 0092 1] Entry Type : 02 [05Dh 0093 2] Device ID : 00FB [05Fh 0095 1] Data Setting : 00 [060h 0096 1] Entry Type : 48 [061h 0097 2] Device ID : 0000 [063h 0099 1] Data Setting : 00 [064h 0100 1] Handle : 00 [065h 0101 2] Source Used Device ID : 00A0 [067h 0103 1] Variety : 01 Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-12-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: add testcase for amd-iommu (IVRS table)Igor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-11-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: whitelist expected blobs for new acpi/q35/ivrs testcaseIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-10-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: add expected blob for DMAR tableIgor Mammedov
[000h 0000 4] Signature : "DMAR" [DMA Remapping table] [004h 0004 4] Table Length : 00000078 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 15 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Host Address Width : 26 [025h 0037 1] Flags : 01 [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00 [030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition] [032h 0050 2] Length : 0040 [034h 0052 1] Flags : 00 [035h 0053 1] Reserved : 00 [036h 0054 2] PCI Segment Number : 0000 [038h 0056 8] Register Base Address : 00000000FED90000 [040h 0064 1] Device Scope Type : 03 [IOAPIC Device] [041h 0065 1] Entry Length : 08 [042h 0066 2] Reserved : 0000 [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF [046h 0070 2] PCI Path : 00,00 [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device] [049h 0073 1] Entry Length : 08 [04Ah 0074 2] Reserved : 0000 [04Ch 0076 1] Enumeration ID : 00 [04Dh 0077 1] PCI Bus Number : 00 [04Eh 0078 2] PCI Path : 00,00 [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device] [051h 0081 1] Entry Length : 08 [052h 0082 2] Reserved : 0000 [054h 0084 1] Enumeration ID : 00 [055h 0085 1] PCI Bus Number : 00 [056h 0086 2] PCI Path : 01,00 [058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device] [059h 0089 1] Entry Length : 08 [05Ah 0090 2] Reserved : 0000 [05Ch 0092 1] Enumeration ID : 00 [05Dh 0093 1] PCI Bus Number : 00 [05Eh 0094 2] PCI Path : 1F,00 [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device] [061h 0097 1] Entry Length : 08 [062h 0098 2] Reserved : 0000 [064h 0100 1] Enumeration ID : 00 [065h 0101 1] PCI Bus Number : 00 [066h 0102 2] PCI Path : 1F,02 [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device] [069h 0105 1] Entry Length : 08 [06Ah 0106 2] Reserved : 0000 [06Ch 0108 1] Enumeration ID : 00 [06Dh 0109 1] PCI Bus Number : 00 [06Eh 0110 2] PCI Path : 1F,03 [070h 0112 2] Subtable Type : 0002 [Root Port ATS Capability] [072h 0114 2] Length : 0008 [074h 0116 1] Flags : 01 [075h 0117 1] Reserved : 00 [076h 0118 2] PCI Segment Number : 0000 Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-9-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: add testcase for intel_iommu (DMAR table)Igor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-8-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: whitelist new expected table tests/data/acpi/q35/DMAR.dmarIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-7-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: update expected tables blobsIgor Mammedov
Update adds CPU entries to MADT/SRAT/FACP and DSDT to cover 288 CPUs. Notable changes are that CPUs with APIC ID 255 and higher use 'Processor Local x2APIC Affinity' structure in SRAT and "Device" element in DSDT. FACP: - Use APIC Cluster Model (V4) : 0 + Use APIC Cluster Model (V4) : 1 SRAT: ... +[1010h 4112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[1011h 4113 1] Length : 10 + +[1012h 4114 1] Proximity Domain Low(8) : 00 +[1013h 4115 1] Apic ID : FE +[1014h 4116 4] Flags (decoded below) : 00000001 + Enabled : 1 +[1018h 4120 1] Local Sapic EID : 00 +[1019h 4121 3] Proximity Domain High(24) : 000000 +[101Ch 4124 4] Clock Domain : 00000000 + +[1020h 4128 1] Subtable Type : 02 [Processor Local x2APIC Affinity] +[1021h 4129 1] Length : 18 + +[1022h 4130 2] Reserved1 : 0000 +[1024h 4132 4] Proximity Domain : 00000001 +[1028h 4136 4] Apic ID : 000000FF +[102Ch 4140 4] Flags (decoded below) : 00000001 + Enabled : 1 +[1030h 4144 4] Clock Domain : 00000000 +[1034h 4148 4] Reserved2 : 00000000 ... +[1320h 4896 1] Subtable Type : 02 [Processor Local x2APIC Affinity] +[1321h 4897 1] Length : 18 + +[1322h 4898 2] Reserved1 : 0000 +[1324h 4900 4] Proximity Domain : 00000001 +[1328h 4904 4] Apic ID : 0000011F +[132Ch 4908 4] Flags (decoded below) : 00000001 + Enabled : 1 +[1330h 4912 4] Clock Domain : 00000000 +[1334h 4916 4] Reserved2 : 00000000 DSDT: ... + Processor (C0FE, 0xFE, 0x00000000, 0x00) + { ... + } + + Device (C0FF) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0xFF) // _UID: Unique ID ... + } + Device (C11F) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x011F) // _UID: Unique ID ... + } APIC: +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 ... +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC] +[81Dh 2077 1] Length : 08 +[81Eh 2078 1] Processor ID : FE +[81Fh 2079 1] Local Apic ID : FE +[820h 2080 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + +[824h 2084 1] Subtable Type : 09 [Processor Local x2APIC] +[825h 2085 1] Length : 10 +[826h 2086 2] Reserved : 0000 +[828h 2088 4] Processor x2Apic ID : 000000FF +[82Ch 2092 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[830h 2096 4] Processor UID : 000000FF ... +[A24h 2596 1] Subtable Type : 09 [Processor Local x2APIC] +[A25h 2597 1] Length : 10 +[A26h 2598 2] Reserved : 0000 +[A28h 2600 4] Processor x2Apic ID : 0000011F +[A2Ch 2604 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[A30h 2608 4] Processor UID : 0000011F + +[A34h 2612 1] Subtable Type : 01 [I/O APIC] +[A35h 2613 1] Length : 0C +[A36h 2614 1] I/O Apic ID : 00 +[A37h 2615 1] Reserved : 00 +[A38h 2616 4] Address : FEC00000 +[A3Ch 2620 4] Interrupt : 00000000 + +[A40h 2624 1] Subtable Type : 02 [Interrupt Source Override] +[A41h 2625 1] Length : 0A +[A42h 2626 1] Bus : 00 +[A43h 2627 1] Source : 00 +[A44h 2628 4] Interrupt : 00000002 +[A48h 2632 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] -[04Bh 0075 1] Length : 0A -[04Ch 0076 1] Bus : 00 -[04Dh 0077 1] Source : 05 -[04Eh 0078 4] Interrupt : 00000005 -[052h 0082 2] Flags (decoded below) : 000D +[A4Ah 2634 1] Subtable Type : 02 [Interrupt Source Override] +[A4Bh 2635 1] Length : 0A +[A4Ch 2636 1] Bus : 00 +[A4Dh 2637 1] Source : 05 +[A4Eh 2638 4] Interrupt : 00000005 +[A52h 2642 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] -[055h 0085 1] Length : 0A -[056h 0086 1] Bus : 00 -[057h 0087 1] Source : 09 -[058h 0088 4] Interrupt : 00000009 -[05Ch 0092 2] Flags (decoded below) : 000D +[A54h 2644 1] Subtable Type : 02 [Interrupt Source Override] +[A55h 2645 1] Length : 0A +[A56h 2646 1] Bus : 00 +[A57h 2647 1] Source : 09 +[A58h 2648 4] Interrupt : 00000009 +[A5Ch 2652 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] -[05Fh 0095 1] Length : 0A -[060h 0096 1] Bus : 00 -[061h 0097 1] Source : 0A -[062h 0098 4] Interrupt : 0000000A -[066h 0102 2] Flags (decoded below) : 000D +[A5Eh 2654 1] Subtable Type : 02 [Interrupt Source Override] +[A5Fh 2655 1] Length : 0A +[A60h 2656 1] Bus : 00 +[A61h 2657 1] Source : 0A +[A62h 2658 4] Interrupt : 0000000A +[A66h 2662 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] -[069h 0105 1] Length : 0A -[06Ah 0106 1] Bus : 00 -[06Bh 0107 1] Source : 0B -[06Ch 0108 4] Interrupt : 0000000B -[070h 0112 2] Flags (decoded below) : 000D +[A68h 2664 1] Subtable Type : 02 [Interrupt Source Override] +[A69h 2665 1] Length : 0A +[A6Ah 2666 1] Bus : 00 +[A6Bh 2667 1] Source : 0B +[A6Ch 2668 4] Interrupt : 0000000B +[A70h 2672 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 -[072h 0114 1] Subtable Type : 04 [Local APIC NMI] -[073h 0115 1] Length : 06 -[074h 0116 1] Processor ID : FF -[075h 0117 2] Flags (decoded below) : 0000 +[A72h 2674 1] Subtable Type : 0A [Local x2APIC NMI] +[A73h 2675 1] Length : 0C +[A74h 2676 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 -[077h 0119 1] Interrupt Input LINT : 01 +[A76h 2678 4] Processor UID : FFFFFFFF +[A7Ah 2682 1] Interrupt Input LINT : 01 +[A7Bh 2683 3] Reserved : 000000 Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-6-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-10-20tests: acpi: q35: test for x2APIC entries in SRATIgor Mammedov
Set -smp 1,maxcpus=288 to test for ACPI code that deal with CPUs with large APIC ID (>255). PS: Test requires KVM and in-kernel irqchip support, so skip test if KVM is not available. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210902113551.461632-5-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-19 15:32:00 +0000