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2010-02-18tcg: Add consistency checks for op definitionsStefan Weil
When compiled with CONFIG_DEBUG_TCG, this code looks for missing, duplicate and wrong entries in the op definitions. Errors will raise an assertion at program start (all checks are done in the initial phase). The current code contains such errors, at least for i386 guest on i386 host. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg: Add tcg_swap_cond.Richard Henderson
Returns the condition as if with swapped comparison operands. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-09tcg/mips: fix crash in tcg_out_qemu_ld()Aurelien Jarno
The address register is overriden when it corresponds to v0 and the fast path is taken, which leads to a crash. Fix that by using the a0 register instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09tcg/mips: implement setcond2Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg/mips: implement setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: move setcond* ops to non-optional sectionAurelien Jarno
setcond is not an optional op, move it to the non-optional section. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: add setcondi pseudo-opAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-07tcg/ppc64: implement setcondmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: proper setcond implementationmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: implement setcond[2]malc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-06tcg-i386: Implement setcond.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-i386: Implement small forward branches.Richard Henderson
There are places, like brcond2, where we know that the destination of a forward branch will be within 127 bytes. Add the R_386_PC8 relocation type to support this. Add a flag to tcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the brcond2 label_next branches; pass along the input flag otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-x86_64: implement setcondRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: add tcg_invert_condRichard Henderson
It is very handy to have a reliable mapping of a condition to its inverse. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: generic support for conditional setRichard Henderson
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: document double-word support opcodes.Richard Henderson
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented. Place these in a new section that clearly indicates that they are not to be emitted by translators. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-15tcg/x86_64: Avoid unnecessary REX.B prefixes.Richard Henderson
The existing P_REXB internal opcode flag unconditionally emits the REX prefix. Technically it's not needed if the register in question is %al, %bl, %cl, %dl. Eliding the prefix requires splitting the P_REXB flag into two, in order to indicate whether the byte register in question is in the REG or the R/M field. Within TCG, the byte register is in the REG field only for stores. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-14tcg/x86_64: Special-case all 32-bit AND operands.Richard Henderson
This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l. Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-12tcg-sparc: Implement ext32[su]_i64Richard Henderson
The 32-bit right-shift instructions is defined to extend the shifted output to 64-bits. A shift count of zero therefore is a simple extension without actually shifting. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement division properly.Richard Henderson
The {div,divu}2 opcodes are intended for systems for which the division instruction produces both quotient and remainder. Sparc is not such a system. Indeed, the remainder must be computed as quot = a / b rem = a - (quot * b) Split out a tcg_out_div32 function that properly initializes Y with the extension of the input to 64-bits. Discard the code that used the 64-bit DIVX on sparc9/sparcv8plus without extending the inputs to 64-bits. Implement remainders in terms of division followed by multiplication. Signed-off-by: Richard Henderson <rth@twiddle.net> [blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Do not remove %o[012] from 'r' constraint.Richard Henderson
Only 'L' constraint needs that. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement add2, sub2, mulu2.Richard Henderson
Add missing 32-bit double-word support opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Add tcg_out_arithc.Richard Henderson
Add a function to handle the register-vs-immediate test for arithmetic. Also, adjust the OP_32_64 macro so that it auto-indents properly. Rename the gen_arith32 label to gen_arith, since it handles 64-bit arithmetic as well. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-27tcg: Add tcg_unsigned_cond.Richard Henderson
Returns an unsigned version of a signed condition; returns the original condition otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Implement brcond2.Richard Henderson
Split out tcg_out_cmp and properly handle immediate arguments. Fix constraints on brcond to match what SUBCC accepts. Add tcg_out_brcond2_i32 for 32-bit host. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.Richard Henderson
The test TCG_TARGET_REG_BITS==64 is exactly the feature that we are checking for, whereas something involving __sparc_v9__ or __sparc_v8plus__ should be reserved for something ISA related, as with SMULX. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Improve tcg_out_movi for sparc64.Richard Henderson
Generate sign-extended 32-bit constants with SETHI+XOR. Otherwise tidy the routine to avoid the need for conditional compilation and code duplication with movi_imm32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Fix imm13 check in movi.Richard Henderson
We were unnecessarily restricting imm13 constants to 12 bits. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-15tcg/ppc64: Fix loading of 32bit constantsmalc
Signed-off-by: malc <av1474@comtv.ru>
2009-12-06TCG: Mac OS X support for ppc64 targetAndreas Faerber
Darwin/ppc64 does not use function descriptors, adapt prologue and tcg_out_call accordingly. GPR2 is available for general use, so let's use it. http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html v2: - Don't mark reserved GPR13 as callee-save. - Move tcg_out_b up. - Fix unused variable warning in prologue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Signed-off-by: malc <av1474@comtv.ru>
2009-12-05S/390 fake TCG implementationAlexander Graf
Qemu won't let us run a KVM target without having host TCG support. Well, for now we don't have any so let's implement a fake target that only stubs out everything. I tried to keep the patch as close to Uli's source as possible, so whenever he feels like it he can easily diff his version against this one. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-01tcg: initial mips supportAurelien Jarno
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> A few words about design choices: * Two registers, at and t0, are reserved for TCG internal use. They are useful for bswap and 64-bit ops. * Most ops supports a constant argument with value 0, which is actually mapped to the zero register. * While the at register is available for constant loading, ops only support a limited range of constants. TCG does a better job doing the register allocation and constant loading by itself. There are plenty of registers available anyway. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-24tcg: fix tcg_regset_{set,reset}_reg with more than 32 registersAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-24tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno
This op only takes two arguments, not two. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14tcg/i386: remove duplicate sar opcodeMagnus Damm
Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-07tcg: improve output logAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04tcg: allocate s->op_dead_iargs dynamicallyAurelien Jarno
Similarly to what is already done in tcg_liveness_analysis() when USE_LIVENESS_ANALYSIS is not set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04tcg: remove dead codeAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04tcg/i386: add support for ext{8,16}u_i32 TCG opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04tcg: add ext{8,16,32}u_i{32,64} TCG opsAurelien Jarno
Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30Revert part of 6692b043198d58a12317009edb98654c6839f043Aurelien Jarno
Committed by accident. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30TCG: fix DEF2 macroAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27tcg/i386: generates dec/inc instead of sub/add when possibleAurelien Jarno
We must take care that dec/inc do not compute CF, which is needed by add2/sub2. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27tcg/i386: optimize and $0xff(ff), regAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27tcg/x86_64: generated dec/inc instead of sub/add when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27tcg/ppc: always use tcg_out_callmalc
Signed-off-by: malc <av1474@comtv.ru>
2009-09-26ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25Suppress some variants of English in commentsStefan Weil
Replace surpress, supress by suppress. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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