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2014-05-12tcg: Require TCG_TARGET_INSN_UNIT_SIZERichard Henderson
Now that all backends do define TCG_TARGET_INSN_UNIT_SIZE, remove the fallback definition. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tci: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-mips: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ia64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
Using a 16-byte aligned structure achieves best results, both for code cleanliness and compiled code size. However, this means that we can't use the trick of encoding the slot number into the low 2 bits. Thankfully, we only ever use slot2, so make that explicit in the names of the relocation functions, and drop the code for other slots. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-s390: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-aarch64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-arm: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-ppc64: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-i386: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Define tcg_insn_unit for code pointersRichard Henderson
To be defined by the tcg backend based on the elemental unit of the ISA. During the transition, allow TCG_TARGET_INSN_UNIT_SIZE to be undefined, which allows us to default tcg_insn_unit to the current uint8_t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Introduce byte pointer arithmetic helpersRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Avoid undefined behaviour patching code at unaligned addressesPeter Maydell
To avoid C undefined behaviour when patching generated code, provide wrappers tcg_patch8/16/32/64 which use the usual memcpy trick, and use them in the i386 backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Avoid stores to unaligned addressesPeter Maydell
Avoid stores to unaligned addresses in TCG code generation, by using the usual memcpy() approach. (Using bswap.h would drag a lot of QEMU baggage into TCG, so it's simpler just to do direct memcpy() here.) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Accept stores of zeroRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Fix small 32-bit moviRichard Henderson
We tested imm13 before discarding garbage high bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Fixup function argument typesRichard Henderson
Use TCGReg everywhere appropriate. Use int32_t for all arguments that may be registers or immediate constants. Merge tcg_out_addi into its only caller. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Hoist common argument loads in tcg_out_opRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Don't handle mov/movi in tcg_out_opRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Tidy check_fit_* testsRichard Henderson
Use sextract instead of raw bit shifting for the tests. Introduce a new check_fit_ptr macro to make it clear we're looking at pointers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Implement muls2_i32Richard Henderson
Using the 32-bit SMUL is a tad more efficient than resorting to extending and using the 64-bit MULX. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Use the RETURN instructionRichard Henderson
Saves one insn per TB exit over JMPL+RESTORE. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Use 64-bit registers with sparcv8plusRichard Henderson
Quite a lot of effort was spent composing and decomposing 64-bit quantities in registers, when we should just create them and leave them as one 64-bit register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Support trunc_shr_i32Richard Henderson
Unlike a 64-bit shift op, allows the output to be in %l or %i registers for sparcv8plus. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg-sparc: Remove most uses of TCG_TARGET_REG_BITSRichard Henderson
Replace with SPARC64 define. Soon even sparcv8plus will use 64-bit register as far as TCG is concerned. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg: Add INDEX_op_trunc_shr_i32Richard Henderson
Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-24Merge remote-tracking branch 'remotes/rth/tags/tcg-next-20140422' into stagingPeter Maydell
Pull tcg 2014-04-22 # gpg: Signature made Tue 22 Apr 2014 22:00:04 BST using RSA key ID 4DD0279B # gpg: Can't check signature: public key not found * remotes/rth/tags/tcg-next-20140422: tcg: Use HOST_WORDS_BIGENDIAN tcg: Fix fallback from muls2_i64 to mulu2_i64 tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32 tcg: Relax requirement for mulu2_i32 on 32-bit hosts tcg-s390: Remove W constraint tcg-sparc: Use the type parameter to tcg_target_const_match tcg-ppc64: Use the type parameter to tcg_target_const_match tcg-aarch64: Remove w constraint tcg: Add TCGType parameter to tcg_target_const_match tcg: Fix out of range shift in deposit optimizations tci: Mask shift counts to avoid undefined behavior tcg: Mask shift quantities while folding tcg: Use "unspecified behavior" for shifts tcg: Fix warning (1 bit signed bitfield entry) and replace int by bool Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-18tcg: Use HOST_WORDS_BIGENDIANRichard Henderson
Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix fallback from muls2_i64 to mulu2_i64Richard Henderson
Brown Bag sez, don't put the fallback code into the wrong function. Also, check for muluh_i64 and use tcg_gen_mulu2_i64 instead of raw ops. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32Richard Henderson
Rather than hard-coding use of mulu2_i32, allow muluh_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Relax requirement for mulu2_i32 on 32-bit hostsRichard Henderson
Instead require either mulu2_i32 or muluh_i32. The code in tcg-op.h already supports looking for both. Previous incomplete conversion? Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-s390: Remove W constraintRichard Henderson
Now redundant with the type parameter to tcg_target_const_match. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-ppc64: Use the type parameter to tcg_target_const_matchRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-aarch64: Remove w constraintRichard Henderson
Now redundant with the type parameter to tcg_target_const_match. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson
Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix out of range shift in deposit optimizationsRichard Henderson
By inspection, for a deposit(x, y, 0, 64), we'd have a shift of (1<<64) and everything else falls apart. But we can reuse the existing deposit logic to get this right. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Mask shift quantities while foldingRichard Henderson
The TCG result would be undefined, but we can at least produce one plausible result and avoid triggering the wrath of analysis tools. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Use "unspecified behavior" for shiftsRichard Henderson
Change the definition such that shifts are not allowed to crash for any input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix warning (1 bit signed bitfield entry) and replace int by boolStefan Weil
Static code analyzers complain about signed bitfields with only a single bit. is_ld is used as a boolean value, so make it bool. ppc64 already used bool for the 2nd argument is_ld of the local function add_qemu_ldst_label. Modify all other TCG targets to do follow this example. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Convert to new ldst opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Move part of softmmu slow path out of lineRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Convert to new ldst helpersRichard Henderson
Still inline, but updated to the new routines. Always use the LE helpers, reusing the bswap between the fast and slot paths. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Reduce code duplication in tcg_out_qemu_ldRichard Henderson
The only differences were in the bswap insns emitted. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Move tlb addend load into tlb readRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Move bswap for store into tlb loadRichard Henderson
Saving at least two cycles per store, and cleaning up the code. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Re-bundle the tlb loadRichard Henderson
This sequencing requires 5 stop bits instead of 6, and has room left over to pre-load the tlb addend, and bswap data prior to being stored. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17tcg-ia64: Optimize small arguments to exit_tbRichard Henderson
Saves one bundle for the common case of exit_tb 0. Signed-off-by: Richard Henderson <rth@twiddle.net>
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