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2010-04-08tcg-hppa: Don't try to calls to non-constant addresses.Richard Henderson
PA-RISC uses procedure descriptors. We'd need to emit a call to the millicode routine $$dyncall. However, this situation doesn't actually arise, since we always have the descriptor available at TCG code generation time. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08tcg-hppa: Fix in/out register overlap in add2/sub2.Richard Henderson
Handle the output log part overlapping the input high parts. Also, improve sub2 to handle some constants the second input low part. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08tcg-hppa: Finish the port.Richard Henderson
Delete inline functions from tcg-target.h that don't need to be there, move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for 0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE support similar to ppc64, with the value stored in a register. Add missing registers to reg_alloc_order. Add support for 12-bit branch relocations. Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori, andi, shifts, rotates, multiply, branches, setcond. Split out TLB reads from qemu_ld and qemu_st; fix argument loading for tlb external calls. Generate the prologue. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08tcg/ia64: fix tlb addend readAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-07tcg/ppc64: Fix typomalc
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06tcg/ppc: Fix typomalc
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06tcg/ppc: Implment bswap16/32malc
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05tcg/mips: use seb/seh instructions on MIPS32R2Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05tcg/mips: fix 64-bit linux-user on big endian MIPSAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05tcg/ppc: Implement eqv, nand and normalc
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook
Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-04tcg/ppc: Fix not_i32malc
Thanks to Alexander Graf for bug report and a good reproducible test case. Signed-off-by: malc <av1474@comtv.ru>
2010-04-01tcg/TODO: remove setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01tcg: initial ia64 supportAurelien Jarno
A few words about design choices: * On IA64, instructions should be grouped by bundle, and dependencies between instructions declared. A first version of this code tried to schedule instructions automatically, but was very complex and too invasive for the current common TCG code (ops not ending at instruction boundaries, code retranslation breaking already generated code, etc.) It was also not very efficient, as dependencies between TCG ops is not available. Instead the option taken by the current implementation does not try to fill the bundle by scheduling instructions, but by providing ops not available as an ia64 instruction, and by offering 22-bit constant loading for most of the instructions. With both options the bundle are filled at approximately the same level. * Up to 128 registers can be affected to a function on IA64, but TCG limits this number to 64, which is actually more than enough. The register affectation is the following: - r0: used to map a constant argument with value 0 - r1: global pointer - r2, r3: internal use - r4 to r6: not used to avoid saving them - r7: env structure - r8 to r11: free for TCG (call clobbered) - r12: stack pointer - r13: thread pointer - r14 to r31: free for TCG (call clobbered) - r32: reserved (return address) - r33: reserved (PFS) - r33 to r63: free for TCG * The IA64 architecture has only 64-bit registers and no 32-bit instructions (the only exception being cmp4). Therefore 64-bit registers and instructions are used for 32-bit ops. The adopted strategy is the same as the ABI, that is the higher 32 bits are undefined. Most ops (and, or, add, shl, etc.) can directly use the 64-bit registers, while some others have to sign-extend (sar, div, etc.) or zero-extend (shr, divu, etc.) the register first. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-29tcg/mips: fix branch offset during retranslationAurelien Jarno
Branch offsets should only be overwritten during relocation, to support partial retranslation. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-28tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil
Commit 86feb1c860dc38e9c89e787c5210e8191800385e did not change all occurrences of INDEX_op_qemu_ld32u for tcg/arm. Please note that I could not test this patch (I have currently no arm system available). Cc: Richard Henderson <rth@twiddle.net> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27tcg-mips: add guest base supportAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27tcg/mips: implement the not_i32 op the same way as gccAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27tcg-mips: implement norAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use not_i32 to implement not_i64.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Change TCGType to an enumeration.Richard Henderson
The TCGType name was already used consistently. Changing it to an enumeration instead of a set of defines aids debugging. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson
Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Name the opcode enumeration.Richard Henderson
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23tcg-hppa: Fix 64-bit argument orderingRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno
There is no need to save r7, it is used to store the address of the env structure and is not modified by GCC. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg: protect div2 in tcg/tcg-opc.hAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: declare internal helpers as const and pureAurelien Jarno
TCG internal helpers only access to the values passed in arguments, and do not modify the CPU internal state. Thus they can be declared as const and pure. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix build with -DNDEBUG in CFLAGSBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/arm: implement andc opAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg: update README with const and pure helpersAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix Sparc host build breakageBlue Swirl
Fix error: CC sparc-bsd-user/op_helper.o In file included from /src/qemu/tcg/tcg.c:158: /src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc
Signed-off-by: malc <av1474@comtv.ru>
2010-03-12Remove TLB from userspacePaul Brook
Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02Add a missing breakAndrzej Zaborowski
2010-03-02tcg/arm: implement setcond2Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: implement setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno
When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-02-27tcg/ppc: Fix right rotationmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23tcg/ppc: Fix typomalc
Signed-off-by: malc <av1474@comtv.ru>
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