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AgeCommit message (Expand)Author
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini
2018-12-26tcg: Improve call argument loadingRichard Henderson
2018-12-26tcg: Record register preferences during livenessRichard Henderson
2018-12-26tcg: Add TCG_OPF_BB_EXITRichard Henderson
2018-12-26tcg: Split out more subroutines from liveness_pass_1Richard Henderson
2018-12-26tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson
2018-12-26tcg: Reindent parts of liveness_pass_1Richard Henderson
2018-12-26tcg: Dump register preference info with livenessRichard Henderson
2018-12-26tcg: Improve register allocation for matching constraintsRichard Henderson
2018-12-26tcg: Add output_pref to TCGOpRichard Henderson
2018-12-26tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson
2018-12-26tcg: Add preferred_reg argument to temp_syncRichard Henderson
2018-12-26tcg: Add preferred_reg argument to temp_loadRichard Henderson
2018-12-26tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson
2018-12-26tcg: Add reachable_code_passRichard Henderson
2018-12-26tcg: Reference count labelsRichard Henderson
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson
2018-12-26tcg: Renumber TCG_CALL_* flagsRichard Henderson
2018-12-26tcg/riscv: Add the target init codeAlistair Francis
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis
2018-12-26tcg/riscv: Add support for the constraintsAlistair Francis
2018-12-26tcg/riscv: Add the tcg target registersAlistair Francis
2018-12-26tcg/riscv: Add the tcg-target.h fileAlistair Francis
2018-12-17tcg: Drop nargs from tcg_op_insert_{before,after}Emilio G. Cota
2018-12-17tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITSAlistair Francis
2018-12-17tcg: Add TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson
2018-12-17tcg/optimize: Optimize bswapRichard Henderson
2018-12-17tcg: Clean up generic bswap64Richard Henderson
2018-12-17tcg: Clean up generic bswap32Richard Henderson
2018-12-17tcg/i386: Add setup_guest_base_seg for FreeBSDRichard Henderson
2018-12-17tcg/i386: Precompute all guest_base parametersRichard Henderson
2018-12-17tcg/i386: Assume 32-bit values are zero-extendedRichard Henderson
2018-12-17tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guestsRichard Henderson
2018-12-17tcg/i386: Propagate is64 to tcg_out_qemu_ld_slow_pathRichard Henderson
2018-12-17tcg/i386: Propagate is64 to tcg_out_qemu_ld_directRichard Henderson
2018-12-17tcg/s390x: Return false on failure from patch_relocRichard Henderson
2018-12-17tcg/ppc: Return false on failure from patch_relocRichard Henderson
2018-12-17tcg/arm: Return false on failure from patch_relocRichard Henderson
2018-12-17tcg/aarch64: Return false on failure from patch_relocRichard Henderson