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2011-03-24tcg/arm: Support host code being compiled for ThumbPeter Maydell
Although the TCG generated code is always in ARM mode, it is possible that the host code was compiled by gcc in Thumb mode (this is often the default for Linux distributions targeting ARM v7 only). Handle this by using BLX imm when doing a call from ARM into Thumb mode. Since BLX imm is not a conditionalisable instruction, we make tcg_out_call() no longer take a condition code; we were only ever using it with COND_AL anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-07tcg: Add support for debugging leakage of temporariesPeter Maydell
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage of temporary variables. Generally any temporaries created by a target while it is translating an instruction should be freed by the end of that instruction; otherwise carefully crafted guest code could cause TCG to run out of temporaries and assert. By calling tcg_check_temp_count() after each instruction we can check that we are not leaking temporaries in this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-20tcg: README, name deposit second argument len/LENEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-20tcg: Define "deposit" as an optional operation.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-12tcg arm/mips/ia64: add a comment about retranslation and cachesAurelien Jarno
Add a comment about cache coherency and retranslation, so that people developping new targets based on existing ones are warned of the issue. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10tcg/arm: improve constant loadingAurelien Jarno
Improve constant loading in two ways: - On all ARM versions, it's possible to load 0xffffff00 = -0x100 using the mvn rd, #0. Fix the conditions. - On <= ARMv6 versions, where movw and movt are not available, load the constants using mov and orr with rotations depending on the constant to load. This is very useful for example to load constants where the low byte is 0. This reduce the generated code size by about 7%. Also fix the coding style at the same time. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-10tcg/ia64: remove an unnecessary stop bitAurelien Jarno
Spotted by Richard Henderson. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-09tcg: fix typo in readmeMike Frysinger
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-09tcg/README: Spelling fixesStefan Weil
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-08tcg/mips: fix branch target change during code retranslationAurelien Jarno
TCG on MIPS was trying to avoid changing the branch offset, but didn't due to a stupid typo. Fix it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix qemu_st64 for big endian targetsAurelien Jarno
Due to a typo, qemu_st64 doesn't properly byteswap the 32-bit low word of a 64 bit word before saving it. This patch fixes that. Acked-by: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-08tcg/arm: fix branch target change during code retranslationAurelien Jarno
QEMU uses code retranslation to restore the CPU state when an exception happens. For it to work the retranslation must not modify the generated code. This is what is currently implemented in ARM TCG. However on CPU that don't have icache/dcache/memory synchronised like ARM, this requirement is stronger and code retranslation must not modify the generated code "atomically", as the cache line might be flushed at any moment (interrupt, exception, task switching), even if not triggered by QEMU. The probability for this to happen is very low, and depends on cache size and associativiy, machine load, interrupts, so the symptoms are might happen randomly. This requirement is currently not followed in tcg/arm, for the load/store code, which basically has the following structure: 1) tlb access code is written 2) conditional fast path code is written 3) branch is written with a temporary target 4) slow path code is written 5) branch target is updated The cache lines corresponding to the retranslated code is not flushed after code retranslation as the generated code is supposed to be the same. However if the cache line corresponding to the branch instruction is flushed between step 3 and 5, and is not flushed again before the code is executed again, the branch target is wrong. In the guest, the symptoms are MMU page fault at a random addresses, which leads to kernel page fault or segmentation faults. The patch fixes this issue by avoiding writing the branch target until it is known, that is by writing only the branch instruction first, and later only the offset. This fixes booting linux guests on ARM hosts (tested: arm, i386, mips, mipsel, sh4, sparc). Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-01tcg-ia64: Fix warning in qemu_ld.Richard Henderson
The usermode version of qemu_ld doesn't used mem_index, leading to set-but-not-used warnings. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Fix address compilation in qemu_st.Richard Henderson
A typo in the usermode address calculation path; R3 used where R2 needed. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Fix tlb read error for 32-bit targets.Richard Henderson
Use ld4 not ld8 for reading the tlb of 32-bit targets. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Implement qemu_ld32.Richard Henderson
The port was not properly merged following 86feb1c860dc38e9c89e787c5210e8191800385e Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg-ia64: Provide default GUEST_BASE.Richard Henderson
Fix compilation error when GUEST_BASE is not defined. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-12-01tcg: Fix default definition of divu_i32 and remu_i32.Richard Henderson
The arguments to tcg_gen_helper32 for these functions were not updated correctly in rev 2bece2c88331f024a46527634e3dd91c71d22141. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-10-30tcg: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-20tcg: Fix compiler error (comparison of unsigned expression)Stefan Weil
When qemu is configured with --enable-debug-tcg, gcc throws this warning (or error with -Werror): tcg/tcg.c:1030: error: comparison of unsigned expression >= 0 is always true Fix it by removing the >= 0 part. The type cast to 'unsigned' catches negative values of op (which should never happen). This is a modification of Hollis Blanchard's patch. Cc: Hollis Blanchard <hollis@penguinppc.org> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-15TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber
3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target compilation in the code path without guest base. Reverting this line fixes the build. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-08-15TCG: Fix Darwin/ppc calling convention recognitionAndreas Färber
5da79c86a3744e3a901c7986c109dd06951befd2 broke compilation on Mac OS X v10.5 ppc. Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize __APPLE__ again as well. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: J?rgen Lock <nox@jelal.kn-bremen.de> Cc: Stefan Weil <weil@mail.berlios.de> Signed-off-by: malc <av1474@comtv.ru>
2010-06-29tcg-s390: new TCG TargetRichard Henderson
Original patch from Ulrich Hecht, further work from Alexander Graf and Richard Henderson. Cc: Ulrich Hecht <uli@suse.de> Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson
We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11tcg: fix DEF macro after commit c61aaf7a388c4ad95d8b546fdb9267dc01183317Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11tcg-s390: Icache flush is a no-op.Richard Henderson
Before gcc 4.2, __builtin___clear_cache doesn't exist, and afterward the gcc s390 backend implements it as nothing. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10tcg-i386: fix andi r, r, 0xffAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10tcg-i386: remove use of _Bool that slipped code reviewAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-10tcg-i386: Merge 64-bit generation.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: get rid of DEF2 in tcg-opc.hAurelien Jarno
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in tcg-opc.h. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: get rid of copy_size in TCGOpDefAurelien Jarno
copy_size is a left-over from the dyngen era, remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson
Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-03tcg-i386: fix a typoAurelien Jarno
Fix a typo introduced by c28b14c694d759f39fe3ae4f8d03b567da5b93f8. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: declare tcg_out_tlb_load() inlineAurelien Jarno
Declare tcg_out_tlb_load() inline so that we don't loose optimisations with commit 8516a04467cb7954cdc32e8b79b4b7df56dccb16. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: Remove some ifdefs in qemu_ld/st.Richard Henderson
Tidy some code by replacing ifdefs by C ifs. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: Split out tlb load function.Richard Henderson
Share some code between qemu_ld and qemu_st. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: Swap order of TLB hit and miss paths.Richard Henderson
Make fallthru be TLB hit and branch be TLB miss. Doing this both improves branch prediction and will allow further cleanup. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: Split out TLB Hit path from qemu_ld/st.Richard Henderson
Splitting out these functions will allow further cleanups. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-02tcg-i386: Tidy data16 prefixes.Richard Henderson
Include it in the opcode as an extension, as with P_EXT or the REX bits in the x86-64 port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28tcg: Use INDEX_op_qemu_ld32 for 32-bit results.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-ia64: Load GUEST_BASE into a register.Richard Henderson
Saves one bundle per memory operation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-ia64: Fix some register usage issues.Richard Henderson
(1) The output registers were not marked call-clobbered, even though they can be modified by called functions. (2) The thread pointer was not marked reserved. (3) R4-R6 are call-saved, but not saved by the prologue. Rather than save them, mark them reserved so that we don't use them. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-hppa: Load GUEST_BASE as an immediate.Richard Henderson
Now that the prologue is generated after GUEST_BASE is fixed, we can load it as an immediate, and also avoid reserving the register if it isn't necessary. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg: Initialize the prologue after GUEST_BASE is fixed.Richard Henderson
This will allow backends to make intelligent choices about how to implement GUEST_BASE. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-i386: Nuke trailing whitespace.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-i386: Use lea for three-operand add.Richard Henderson
The result is shorter than the mov+add that TCG would otherwise generate for us. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-i386: Tidy lea.Richard Henderson
Implement full modrm+sib addressing mode processing. Use that in qemu_ld/st to output the LEA. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-21tcg-i386: Tidy xchg.Richard Henderson
Define and use OPC_XCHG_ax_r32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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