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2010-03-13Fix Sparc host build breakageBlue Swirl
Fix error: CC sparc-bsd-user/op_helper.o In file included from /src/qemu/tcg/tcg.c:158: /src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc
Signed-off-by: malc <av1474@comtv.ru>
2010-03-12Remove TLB from userspacePaul Brook
Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02Add a missing breakAndrzej Zaborowski
2010-03-02tcg/arm: implement setcond2Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: implement setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno
When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-02-27tcg/ppc: Fix right rotationmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23tcg/ppc: Fix typomalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc64: Use C90 style commentsmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc: Implement some of the optional opsmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: fix assertion with --enable-debugJay Foad
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix the following assertion failure: qemu-alpha: tcg/tcg.c:1055: tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ORC.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ANDC.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ORC.Richard Henderson
Previously ORC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg: Optional target implementation of ANDC.Richard Henderson
Previously ANDC was always implemented by tcg-op.h with an explicit NOT opcode. Allow a target implementation. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement not.Richard Henderson
The fallback implementation of "ret = arg1 ^ -1" isn't ideal because of the extra tcg op to load the minus one. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement neg.Richard Henderson
The fallback implementation of "ret = 0 - arg1" isn't ideal, first because of the extra tcg op to load the zero, and second because we fail to handle zero as %g0 for arg1 of the sub. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20Use ppc host calling convention definitions to set ↵Juergen Lock
TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. New version after malc's comments. (This avoids having to do #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__ for the third case.) Submitted by: Andreas Tobler <andreast@fgznet.ch> (original version) Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: malc <av1474@comtv.ru>
2010-02-18tcg: Add consistency checks for op definitionsStefan Weil
When compiled with CONFIG_DEBUG_TCG, this code looks for missing, duplicate and wrong entries in the op definitions. Errors will raise an assertion at program start (all checks are done in the initial phase). The current code contains such errors, at least for i386 guest on i386 host. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg: Add tcg_swap_cond.Richard Henderson
Returns the condition as if with swapped comparison operands. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-09tcg/mips: fix crash in tcg_out_qemu_ld()Aurelien Jarno
The address register is overriden when it corresponds to v0 and the fast path is taken, which leads to a crash. Fix that by using the a0 register instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-09tcg/mips: implement setcond2Aurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg/mips: implement setcondAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: move setcond* ops to non-optional sectionAurelien Jarno
setcond is not an optional op, move it to the non-optional section. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-08tcg: add setcondi pseudo-opAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-07tcg/ppc64: implement setcondmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: proper setcond implementationmalc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: implement setcond[2]malc
Signed-off-by: malc <av1474@comtv.ru>
2010-02-06tcg-i386: Implement setcond.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-i386: Implement small forward branches.Richard Henderson
There are places, like brcond2, where we know that the destination of a forward branch will be within 127 bytes. Add the R_386_PC8 relocation type to support this. Add a flag to tcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the brcond2 label_next branches; pass along the input flag otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg-x86_64: implement setcondRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: add tcg_invert_condRichard Henderson
It is very handy to have a reliable mapping of a condition to its inverse. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: generic support for conditional setRichard Henderson
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06tcg: document double-word support opcodes.Richard Henderson
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented. Place these in a new section that clearly indicates that they are not to be emitted by translators. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-15tcg/x86_64: Avoid unnecessary REX.B prefixes.Richard Henderson
The existing P_REXB internal opcode flag unconditionally emits the REX prefix. Technically it's not needed if the register in question is %al, %bl, %cl, %dl. Eliding the prefix requires splitting the P_REXB flag into two, in order to indicate whether the byte register in question is in the REG or the R/M field. Within TCG, the byte register is in the REG field only for stores. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-14tcg/x86_64: Special-case all 32-bit AND operands.Richard Henderson
This avoids an unnecessary REX.W prefix when dealing with AND operands that fit into a 32-bit quantity. The most common change actually seen is movz[wb]q -> movz[wb]l. Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-12tcg-sparc: Implement ext32[su]_i64Richard Henderson
The 32-bit right-shift instructions is defined to extend the shifted output to 64-bits. A shift count of zero therefore is a simple extension without actually shifting. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement division properly.Richard Henderson
The {div,divu}2 opcodes are intended for systems for which the division instruction produces both quotient and remainder. Sparc is not such a system. Indeed, the remainder must be computed as quot = a / b rem = a - (quot * b) Split out a tcg_out_div32 function that properly initializes Y with the extension of the input to 64-bits. Discard the code that used the 64-bit DIVX on sparc9/sparcv8plus without extending the inputs to 64-bits. Implement remainders in terms of division followed by multiplication. Signed-off-by: Richard Henderson <rth@twiddle.net> [blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Do not remove %o[012] from 'r' constraint.Richard Henderson
Only 'L' constraint needs that. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement add2, sub2, mulu2.Richard Henderson
Add missing 32-bit double-word support opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Add tcg_out_arithc.Richard Henderson
Add a function to handle the register-vs-immediate test for arithmetic. Also, adjust the OP_32_64 macro so that it auto-indents properly. Rename the gen_arith32 label to gen_arith, since it handles 64-bit arithmetic as well. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-27tcg: Add tcg_unsigned_cond.Richard Henderson
Returns an unsigned version of a signed condition; returns the original condition otherwise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Implement brcond2.Richard Henderson
Split out tcg_out_cmp and properly handle immediate arguments. Fix constraints on brcond to match what SUBCC accepts. Add tcg_out_brcond2_i32 for 32-bit host. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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