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path: root/tcg/riscv/tcg-target.inc.c
AgeCommit message (Expand)Author
2019-07-09tcg/riscv: Fix RISC-VH host build failureAlistair Francis
2019-06-10cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson
2019-06-10tcg: Create struct CPUTLBRichard Henderson
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson
2019-04-24tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson
2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson
2018-12-26tcg/riscv: Add the target init codeAlistair Francis
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis
2018-12-26tcg/riscv: Add support for the constraintsAlistair Francis
2018-12-26tcg/riscv: Add the tcg target registersAlistair Francis
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