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AgeCommit message (Expand)Author
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook
2010-04-04tcg/ppc: Fix not_i32malc
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson
2010-03-26tcg: Name the opcode enumeration.Richard Henderson
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc
2010-02-27tcg/ppc: Fix right rotationmalc
2010-02-23tcg/ppc: Fix typomalc
2010-02-22tcg/ppc: Implement some of the optional opsmalc
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc
2010-02-20Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARG...Juergen Lock
2010-02-07tcg/ppc32: proper setcond implementationmalc
2010-02-07tcg/ppc32: implement setcond[2]malc
2009-09-27tcg/ppc: always use tcg_out_callmalc
2009-09-06When targeting PPU use rlwinm instead of andi. if possiblemalc
2009-07-20Fix rbase initializationmalc
2009-07-18PPC 32/64 GUEST_BASE supportmalc
2009-07-18Fix LHZX opcode valuemalc
2009-04-11Whack [LS]MWmalc
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc
2009-03-08Prune unused TCG_AREGsblueswir1
2009-02-11Add missing r24..r26 to calle save registersmalc
2009-01-26R13 is reserved for small data area pointer by SVR4 PPC ABImalc
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
2008-12-10Introduce and use cache-utils.[ch]malc
2008-11-18Preliminary AIX supportmalc
2008-11-12Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSETmalc
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir1
2008-09-22Avoid clobbering input register in qemu_ld64+bswap+useronly casemalc
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir1
2008-08-21Relax qemu_ld/st constraints for !SOFTMMU casemalc
2008-08-03Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)malc
2008-08-03Preliminary MacOS X on PPC32 supportmalc
2008-07-29On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64malc
2008-07-28Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc
2008-07-23Provide extNs_M instructionsmalc
2008-07-03Fuse EQ and NE handling in tcg_out_brcond2malc
2008-07-03Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)malc
2008-06-23According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatilemalc
2008-06-23Shuffle contents of tcg_target_reg_alloc_ordermalc
2008-06-18Save LR into proper place on callers stack framemalc
2008-06-12Reimplement brcond2 and refactor brcondmalc
2008-06-10Remove stray variablemalc
2008-06-09Use rem/div[u]_i32 drop div[u]2_i32malc
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