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AgeCommit message (Expand)Author
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil
2011-09-17tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil
2011-09-09tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth
2011-08-22tcg/ppc64: fix 16/32 mixupmalc
2011-08-22tcg/ppc64: implement not_i32/64 and ext32u_i64malc
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson
2011-06-28TCG/PPC: use stack for TCG tempsBlue Swirl
2011-06-28tcg/ppc64: Remove tcg_out_addimalc
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl
2010-08-15TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson
2010-04-07tcg/ppc64: Fix typomalc
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson
2010-03-26tcg: Name the opcode enumeration.Richard Henderson
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc
2010-02-22tcg/ppc64: Use C90 style commentsmalc
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
2010-02-07tcg/ppc64: implement setcondmalc
2009-12-15tcg/ppc64: Fix loading of 32bit constantsmalc
2009-12-06TCG: Mac OS X support for ppc64 targetAndreas Faerber
2009-11-24tcg/ppc64,x86_64: fix constraints of op_qemu_st64Aurelien Jarno
2009-07-18PPC 32/64 GUEST_BASE supportmalc
2009-07-18Fix LHZX opcode valuemalc
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc
2009-04-11Whack [LS]MWmalc
2009-03-08Prune unused TCG_AREGsblueswir1
2009-02-11Add missing r24..r26 to callee save registersmalc
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
2008-12-10Introduce and use cache-utils.[ch]malc
2008-11-12Avoid compiler warningmalc
2008-11-11Fix alignment problem with some 64bit load/store instructionsmalc
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir1
2008-10-02Optimize 64 bit bswapmalc
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir1
2008-08-20Relax qemu_ld/st constraints for !SOFTMMU casemalc
2008-08-20Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap casemalc
2008-08-20Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 casemalc
2008-08-20Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warningmalc
2008-07-28Immediate versions of some operationsmalc
2008-07-28Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc
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