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2013-11-30tcg-ppc64: Use qemu_getauxvalRichard Henderson
Allow host detection on linux systems without glibc 2.16 or later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Support new ldst opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Convert to le/be ldst helpersRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Use TCGMemOp within qemu_ldst routinesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-ldst.hRichard Henderson
Move TCGLabelQemuLdst and related stuff out of tcg.h. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Add _noaddr functions for emitting forward branchesRichard Henderson
... rather than open-coding this stuff through the file. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Streamline tcg_out_tlb_readRichard Henderson
Less conditional compilation. Merge an add insn with the indexed memory load insn. Load the tlb addend earlier. Avoid the address update memory form. Fix a bug in not allowing large enough tlb offsets for some guests. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Implement tcg_register_jitRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Handle long offsets betterRichard Henderson
Previously we'd only handle 16-bit offsets from memory operand without falling back to indexed, but it's easy to use ADDIS to handle full 32-bit offsets. This also lets us unify code that existed inline in tcg_out_op for handling addition of large constants. The new R2 temporary was marked reserved for the AIX calling convention, but the register really is call-clobbered and since tcg generated code has no use for a TOC, it's available for use. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Tidy register allocation orderRichard Henderson
Remove conditionalization from tcg_target_reg_alloc_order, relying on reserved_regs to prevent register allocation that shouldn't happen. So R11 is now present in reg_alloc_order for __APPLE__, but also now reserved. Sort reg_alloc_order into call-saved, call-clobbered, and parameters. This reduces the effect of values getting spilled and reloaded before function calls. Whether or not it is reserved, R2 (TOC) is always call-clobbered. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Look through a constant function descriptorRichard Henderson
Especially in the user-only configurations, a direct branch into the executable may be in range. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Fold constant call address into descriptor loadRichard Henderson
Eliminates one insn per call: : lis r2,4165 -: ori r2,r2,59616 -: ld r0,0(r2) +: ld r0,-5920(r2) : mtctr r0 -: ld r2,8(r2) +: ld r2,-5912(r2) : bctrl Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Don't load the static chain from TCGRichard Henderson
There are no helpers that require the static chain. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Avoid code for nop moveRichard Henderson
While these are rare from code that's been through the optimizer, it's not uncommon within the tcg backend. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Use tcg_out64Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Use TCG_REG_Rn constantsRichard Henderson
Instead of bare N, for clarity. The only (intentional) exception made is for insns that encode R|0, i.e. when R0 encoded into the insn is interpreted as zero not the contents of the register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: More use of TAI and SAI helper macrosRichard Henderson
Finish conversion of all memory operations. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-25tcg-ppc64: Reformat tcg-target.cRichard Henderson
Whitespace and brace changes only. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02exec: Split softmmu_defs.hRichard Henderson
The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change relocation offsets to intptr_tRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-ppc64: Implement muluh, mulshRichard Henderson
Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-ppc64: Don't implement remRichard Henderson
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: rotr_i32 rotates wrong amountAnton Blanchard
rotr_i32 calculates the amount to left shift and puts it into a temporary, but then doesn't use it when doing the shift. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix add2_i64Anton Blanchard
add2_i64 was adding the lower double word to the upper double word of each input. Fix this so we add the lower double words, then the upper double words with carry propagation. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: bswap64 rotates output 32 bitsAnton Blanchard
If our input and output is in the same register, bswap64 tries to undo a rotate of the input. This just ends up rotating the output. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix RLDCL opcodeAnton Blanchard
The rldcl instruction doesn't have an sh field, so the minor opcode is shifted 1 bit. We were using the XO30 macro which shifted the minor opcode 2 bits. Remove XO30 and add MD30 and MDS30 macros which match the Power ISA categories. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Handle deposit of zeroRichard Henderson
The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement mulu2/muls2_i64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement add2/sub2_i64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use getauxval for ISA detectionRichard Henderson
Glibc 2.16 includes an easy way to get feature bits previously buried in /proc or the program startup auxiliary vector. Use it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement movcondRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use ISEL for setcondRichard Henderson
There are a few simple special cases that should be handled first. Break these out to subroutines to avoid code duplication. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use MFOCRF instead of MFCRRichard Henderson
It takes half the cycles to read one CR register instead of all 8. This is a backward compatible addition to the ISA, so chips prior to Power 2.00 spec will simply continue to read the entire CR register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Cleanup i32 constants to tcg_out_cmpRichard Henderson
Nothing else in the call chain ensures that these constants don't have garbage in the high bits. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use TCGType throughout comparesRichard Henderson
The optimization/bug being fixed is that tcg_out_cmp was not applying the right type to loading a constant, in the case it can't be implemented directly. Rather than recomputing the TCGType enum from the arch64 bool, pass around the original TCGType throughout. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use I constraint for mulRichard Henderson
The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement depositRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Handle constant inputs for some compound logicalsRichard Henderson
Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement compound logicalsRichard Henderson
Mostly copied from the ppc32 port. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap16 and bswap32Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement rotatesRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Streamline qemu_ld/st insn selectionRichard Henderson
Using a table to look up insns of the right width and sign. Include support for the Power 2.06 LDBRX and STDBRX insns. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use automatic implementation of ext32u_i64Richard Henderson
The enhancements to and immediate obviate this. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve and_i64 with constantRichard Henderson
Use RLDICL and RLDICR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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