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2013-07-09tcg-ppc64: Don't implement remRichard Henderson
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: rotr_i32 rotates wrong amountAnton Blanchard
rotr_i32 calculates the amount to left shift and puts it into a temporary, but then doesn't use it when doing the shift. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix add2_i64Anton Blanchard
add2_i64 was adding the lower double word to the upper double word of each input. Fix this so we add the lower double words, then the upper double words with carry propagation. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: bswap64 rotates output 32 bitsAnton Blanchard
If our input and output is in the same register, bswap64 tries to undo a rotate of the input. This just ends up rotating the output. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix RLDCL opcodeAnton Blanchard
The rldcl instruction doesn't have an sh field, so the minor opcode is shifted 1 bit. We were using the XO30 macro which shifted the minor opcode 2 bits. Remove XO30 and add MD30 and MDS30 macros which match the Power ISA categories. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Handle deposit of zeroRichard Henderson
The TCG optimizer does great work when inserting constants, being able to fold the open-coded deposit expansion to just an AND or an OR. Avoid a bit the regression caused by having the deposit opcode by expanding deposit of zero as an AND. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement mulu2/muls2_i64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement add2/sub2_i64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use getauxval for ISA detectionRichard Henderson
Glibc 2.16 includes an easy way to get feature bits previously buried in /proc or the program startup auxiliary vector. Use it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement movcondRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use ISEL for setcondRichard Henderson
There are a few simple special cases that should be handled first. Break these out to subroutines to avoid code duplication. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use MFOCRF instead of MFCRRichard Henderson
It takes half the cycles to read one CR register instead of all 8. This is a backward compatible addition to the ISA, so chips prior to Power 2.00 spec will simply continue to read the entire CR register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Cleanup i32 constants to tcg_out_cmpRichard Henderson
Nothing else in the call chain ensures that these constants don't have garbage in the high bits. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use TCGType throughout comparesRichard Henderson
The optimization/bug being fixed is that tcg_out_cmp was not applying the right type to loading a constant, in the case it can't be implemented directly. Rather than recomputing the TCGType enum from the arch64 bool, pass around the original TCGType throughout. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use I constraint for mulRichard Henderson
The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement depositRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Handle constant inputs for some compound logicalsRichard Henderson
Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement compound logicalsRichard Henderson
Mostly copied from the ppc32 port. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap16 and bswap32Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement rotatesRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Streamline qemu_ld/st insn selectionRichard Henderson
Using a table to look up insns of the right width and sign. Include support for the Power 2.06 LDBRX and STDBRX insns. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use automatic implementation of ext32u_i64Richard Henderson
The enhancements to and immediate obviate this. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve and_i64 with constantRichard Henderson
Use RLDICL and RLDICR. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve and_i32 with constantRichard Henderson
Use RLWINM Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Tidy or and xor patterns.Richard Henderson
Handle constants in common code; we'll want to reuse that later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Allow constant first argument to subRichard Henderson
Using SUBFIC for 16-bit signed constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve constant add and sub ops.Richard Henderson
Improve constant addition -- previously we'd emit useless addi with 0. Use new constraints to force the driver to pull full 64-bit constants into a register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Rearrange integer constant constraintsRichard Henderson
We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Cleanup tcg_out_moviRichard Henderson
The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing a signed 32-bit quantity against an unsigned 32-bit quantity. When possible, use addi+oris for 32-bit unsigned constants. Otherwise, standardize on addi+oris+ori instead of addis+ori+rldicl. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Fix setcond_i32Richard Henderson
We weren't ignoring the high 32 bits during a NE comparison. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use TAI and SAIRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_shri64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_shli64Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_ext32uRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_rlwRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use TCGReg everywhereRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19janitor: add guards to headersPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell
GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: remove obsolete jmp opAurelien Jarno
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg: Introduce movcondRichard Henderson
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-06-24TCG: Fix compile breakage in tcg_dump_opsAlexander Graf
Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convert all users (notably missing the ppc ones) to it. Fix them to the new syntax. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: malc <av1474@comtv.ru>
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