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2024-06-19tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointersRichard Henderson
Simplify the logic for two-part, 32-bit pc-relative addresses. Rather than assume all such fit in int32_t, do some arithmetic and assert a result, do some arithmetic first and then check to see if the pieces are in range. Cc: qemu-stable@nongnu.org Fixes: dacc51720db ("tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi") Reviewed-by: Song Gao <gaosong@loongson.cn> Reported-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Enable v256 with LASXRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_vec_opRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjukN in tcg_out_vec_opRichard Henderson
Fixes a bug in the immediate shifts, because the exact encoding depends on the element size. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Remove temp_vec from tcg_out_vec_opRichard Henderson
Use TCG_VEC_TMP0 directly. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st}Richard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjvk in tcg_out_vec_opRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_addsub_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_addsub_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupi_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupm_vecRichard Henderson
Each element size has a different encoding, so code cannot be shared in the same way as with tcg_out_dup_vec. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dup_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_dup_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support TCG_TYPE_V64Richard Henderson
We can implement this with fld_d, fst_d for load and store, and then use the normal v128 operations in registers. This will improve support for guests which use v64. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Handle i32 and i64 moves between gr and frRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use fp load/store for I32 and I64 into vector regsRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Import LASX, FP insnsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-22tcg: Introduce TCG_TARGET_HAS_tst_vecRichard Henderson
Prelude to supporting TCG_COND_TST* in vector comparisons. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-15tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regsRichard Henderson
TCG register spill/fill uses tcg_out_ld/st with all types, not necessarily going through INDEX_op_{ld,st}_vec. Cc: qemu-stable@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn>
2024-02-03tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson
Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson
Define as 0 for all tcg backends. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03tcg/loongarch64: Set vector registers call clobberedRichard Henderson
Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-stable@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org>
2023-11-21tcg/loongarch64: Fix tcg_out_mov() AbortedSong Gao
On LoongArch host, we got an Aborted from tcg_out_mov(). qemu-x86_64 configure with '--enable-debug'. > (gdb) b /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > Breakpoint 1 at 0x2576f0: file /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc, line 312. > (gdb) run hello [...] > Thread 1 "qemu-x86_64" hit Breakpoint 1, tcg_out_mov (s=0xaaaae91760 <tcg_init_ctx>, type=TCG_TYPE_V128, ret=TCG_REG_V2, > arg=TCG_REG_V0) at /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > 312 g_assert_not_reached(); > (gdb) bt > #0 tcg_out_mov (s=0xaaaae91760 <tcg_init_ctx>, type=TCG_TYPE_V128, ret=TCG_REG_V2, arg=TCG_REG_V0) > at /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312 > #1 0x000000aaaad0fee0 in tcg_reg_alloc_mov (s=0xaaaae91760 <tcg_init_ctx>, op=0xaaaaf67c20) at ../tcg/tcg.c:4632 > #2 0x000000aaaad142f4 in tcg_gen_code (s=0xaaaae91760 <tcg_init_ctx>, tb=0xffe8030340 <code_gen_buffer+197328>, > pc_start=4346094) at ../tcg/tcg.c:6135 [...] > (gdb) c > Continuing. > ** > ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov: code should not be reached > Bail out! ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov: code should not be reached > > Thread 1 "qemu-x86_64" received signal SIGABRT, Aborted. > 0x000000fff7b1c390 in raise () from /lib64/libc.so.6 > (gdb) q Fixes: 16288ded94 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231120065916.374045-1-gaosong@loongson.cn>
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Implement neg opcodesRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Use cpuinfo.hRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
2023-11-06tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson
Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr + 0" in that case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
2023-10-22tcg/loongarch64: Use tcg_use_softmmuRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-6-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-04tcg/loongarch64: Fix buid errorgaosong
Fix: In file included from ../tcg/tcg.c:735: /home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc: In function ‘tcg_out_vec_op’: /home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc:1855:9: error: a label can only be part of a statement and a declaration is not a statement TCGCond cond = args[3]; ^~~~~~~ Signed-off-by: gaosong <gaosong@loongson.cn> Message-Id: <20230926075819.3602537-1-gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson
This hook may emit code at the beginning of the TB. Suggested-by: Jordan Niethe <jniethe5@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-16tcg/loongarch64: Implement 128-bit load & storeJiajie Chen
If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores. Signed-off-by: Jiajie Chen <c@jia.je> Message-Id: <20230908022302.180442-17-c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-16-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen
Lower the following ops: - rotrv_vec - rotlv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-15-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector shift integer opsJiajie Chen
Lower the following ops: - shli_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-14-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-13-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector shift vector opsJiajie Chen
Lower the following ops: - shlv_vec - shrv_vec - sarv_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-12-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector saturated opsJiajie Chen
Lower the following ops: - ssadd_vec - usadd_vec - sssub_vec - ussub_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-11-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector min max opsJiajie Chen
Lower the following ops: - smin_vec - smax_vec - umin_vec - umax_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-10-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower mul_vec to vmulJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-9-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower neg_vec to vnegJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-8-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower vector bitwise operationsJiajie Chen
Lower the following ops: - and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-7-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen
Lower the following ops: - add_vec - sub_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-6-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-5-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen
Pass vece to tcg_target_const_match() to allow correct interpretation of const args of vector ops. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230908022302.180442-4-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen
LSX support on host cpu is detected via hwcap. Lower the following ops to LSX: - dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-3-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15tcg/loongarch64: Import LSX instructionsJiajie Chen
Add opcodes and encoder functions for LSX. Generated from https://github.com/jiegec/loongarch-opcodes/tree/qemu-lsx. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-2-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24tcg: Introduce negsetcond opcodesRichard Henderson
Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-22 20:15:07 +0000