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AgeCommit message (Expand)Author
2010-04-19tcg/arm: remove useless register tests in qemu_ld/stAurelien Jarno
2010-04-19tcg/arm: bswap arguments in qemu_ld/st if neededAurelien Jarno
2010-04-19tcg/arm: use ext* ops in qemu_ldAurelien Jarno
2010-04-19tcg/arm: remove conditional argument for qemu_ld/stAurelien Jarno
2010-04-19tcg/arm: add bswap opsAurelien Jarno
2010-04-19tcg/arm: add ext16u opAurelien Jarno
2010-04-19tcg/arm: add rotation opsAurelien Jarno
2010-04-19tcg/arm: use the blx instruction when possibleAurelien Jarno
2010-04-19tcg/arm: sxtb and sxth are available starting with ARMv6Aurelien Jarno
2010-04-19tcg/arm: add variables to define the allowed instructions setAurelien Jarno
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno
2010-04-19tcg/arm: replace integer values by registers enumAurelien Jarno
2010-04-19tcg/arm: remove store signed functionsAurelien Jarno
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno
2010-04-19tcg/arm: remove SAVE_LR codeAurelien Jarno
2010-03-28tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
2010-03-26tcg: Name the opcode enumeration.Richard Henderson
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
2010-03-20tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno
2010-03-20tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno
2010-03-13tcg/arm: implement andc opAurelien Jarno
2010-03-13tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno
2010-03-12Remove TLB from userspacePaul Brook
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno
2010-03-02Add a missing breakAndrzej Zaborowski
2010-03-02tcg/arm: implement setcond2Aurelien Jarno
2010-03-02tcg/arm: implement setcondAurelien Jarno
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
2009-09-26ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues
2009-09-25Suppress some variants of English in commentsStefan Weil
2009-08-25ARM back-end: Fix encode_immLaurent Desnogues
2009-08-22ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues
2009-08-22ARM back-end: Add TCG notLaurent Desnogues
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela
2009-07-18this patch improves the ARM back-end in the following way:Laurent Desnogues
2009-07-17Userspace guest address offsettingPaul Brook
2009-07-17ARM host fixesPaul Brook
2009-03-13tcg: rename bswap_i32/i64 functionsaurel32
2009-03-10tcg-arm: fix qemu_ld64aurel32
2009-03-08Prune unused TCG_AREGsblueswir1
2008-12-07Fix 64-bit targets compilation on ARM host.balrog
2008-12-01arm: Don't potentially overwrite input registers in add2, sub2.balrog
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