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path: root/tcg/arm/tcg-target.h
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2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson
Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-19tcg/arm: add bswap opsAurelien Jarno
Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add ext16u opAurelien Jarno
Add an ext16u op, either using the uxth instruction on ARMv6+ or two shifts on previous ARM versions. In both cases the result use the same number or less instructions than the pure TCG version. Also move all sign extension code to separate functions, so that they can be reused in other parts of the code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add rotation opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno
As specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno
Instead of writing very compact code, declare all registers that are clobbered or reserved one by one. This makes the code easier to read. Also declare all the 16 registers to TCG, and mark pc as reserved. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: implement andc opAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-22ARM back-end: Add TCG notLaurent Desnogues
this patch: - implements TCG not. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-18this patch improves the ARM back-end in the following way:Laurent Desnogues
- use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-17Userspace guest address offsettingPaul Brook
Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17ARM host fixesPaul Brook
Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-03-13tcg: rename bswap_i32/i64 functionsaurel32
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08Prune unused TCG_AREGsblueswir1
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01Use libgcc __clear_cache to clean icache, when available.balrog
Calling the clear cache syscall directly generates an illegal instruction on some (armv4) kernels. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5843 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-23Define TCG_TARGET_CALL_STACK_OFFSET on arm.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4541 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-20Implement neg_i32, clean-up.balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-19ARM host support for TCG targets.balrog
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162
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